MC68EC030FE40C Datasheet, PDF (12/36 Pages) Freescale Semiconductor, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting
of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with
address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed of
the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry),
and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the
MC68EC030 whenever a cache miss occurs; using the burst transfer capability, up to four long words can
be filled in one burst operation. The caches cannot be manipulated directly by the programmer except by
the use of the CACR, which provides cache clearing and cache entry clearing facilities. The caches can
also be enabled/disabled by this register. Finally, the system hardware can disable the on-chip caches at
any time by asserting the CDIS signal.
FFF A
CC C 3
21 0 1
LONG WORD
SELECT
TAG
INDEX
AA AAAAAAAAAAAAAAAAAAAAAA
2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ^{ACCESS ADDRESS}
32 1098765432109876543210
TAG
V VVV
1 OF 16
SELECT
TAG REPLACE
VALID
COMPARATOR
LINE HIT
ENTRY HIT
DATA FROM INSTRUCTION
CACHE DATA BUS
DATA TO INSTRUCTION
CACHE HOLDING REGISTER
CACHE CONTROL LOGIC
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
Figure 6. On-Chip Instruction Cache Organization
12
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