MC68EC030FE40C Datasheet, PDF (11/36 Pages) Freescale Semiconductor, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
cpBCC
cpDBcc
cpGEN
Coprocessor Instructions
Branch Conditionally
Test Coprocessor Condition,
Decrement and Branch
Coprocessor General Instruction
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally
Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds
checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)
offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030
can be used on the MC68040 for even more performance. The memory management unit (MMU)
instructions of the MC68030, and MC68040 are not supported by the MC68EC030.
INSTRUCTION AND DATA CACHES
Studies have shown that typical programs spend most of their execution time in a few main routines or
tight loops. This phenomenon, known as locality of reference, has an impact on program performance.
The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can be
used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to
provide the system with two on-chip caches, one for instructions and one for data.
MC68EC030 CACHE GOALS
Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030
embedded controller caches. The first design goal was to reduce the external bus activity of the CPU
even more than was accomplished with the MC68020. The second design goal was to increase effective
CPU throughput as larger memory sizes or slower memories increased average access time. By placing a
high-speed cache between the controller and the rest of the memory system, the effective memory
access time becomes:
tacc =Rh*tcache + (1-Rh)*text
where tacc is the effective system access time, tcache is the cache access time, text is the access time of
the rest of the system, and Rh is the hit ratio or the percentage of time that the data is found in the cache.
Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial
CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower
and less expensive memories can be used for the same controller performance.
The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are
accessed in less time than is required for external accesses, providing improvement in the access time for
items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be
found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time
required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time
for items found in the caches even further. Third, the autonomous nature of the caches allows instruction
stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.
The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently
so that several internal instructions (those that do not require any external accesses) can execute while
the controller is performing an external access for a previous instruction.
INSTRUCTION CACHE
MOTOROLA
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