MC68EC030FE40C Datasheet, PDF (2/36 Pages) Freescale Semiconductor, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
INTRODUCTION
The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.
The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-
chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.
The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure
1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.
CONTROLLER
CLOCK (40 MHz)
20 MHz
OSC.
MC88916
3
BUS CLOCK
(20 MHz)
BUS CLOCK
(40 MHz)
BUS CLOCK
(80 MHz)
MC68EC030
(40 MHz)
Figure 1. MC68EC030 Clock Circuitry
The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing
2
F^Mor^CM⁶⁸o^Ere^C0In³⁰for^Tm^Ea^Ct^Hio^Nn^ICO^An^LTh^Dis^ATP^Aroduct,
MOTOROLA
Go to: www.freescale.com