MC9S12XEP100_10 Datasheet, PDF (231/1324 Pages) Freescale Semiconductor, Inc – HCS12X Microcontrollers

Chapter 4 Memory Protection Unit (S12XMPUV1)
4.3.1.1 MPU Flag Register (MPUFLG)
Address: Module Base + 0x0000
7
6
5
4
3
2
1
0
R
WPF
NEXF
0
0
0
0
SVSF
AEF
W
Reset
0
0
0
0
0
0
0
0
Figure 4-3. MPU Flag Register (MPUFLG)
Read: Anytime
Write: Write of 1 clears flag, write of 0 ignored
Table 4-3. MPUFLG Field Descriptions
Field
7
AEF
6
WPF
5
NEXF
0
SVSF
Description
Access Error Flag — This bit is the CPU access error interrupt flag. It is set if a CPU access violation has
occurred. At the same time this bit is set, all the other status flags in this register and the access violation
address bits in the MPUASTATn registers are captured. Clear this flag by writing a one.
Note: If a CPU access error is flagged and both the WPF bit and the NEXF bit are zero, the access violation
was caused by an access to memory not covered by the MPU descriptors.
Note: While this bit is set, the CPU in supervisor state (“Master 0”) can read from and write to the peripheral
register space even if there is no memory protection descriptor explicitly allowing this. This is to prevent
the case that the CPU cannot clear the AEF bit if the registers are write protected for the CPU in
supervisor state.
Note: This bit should only be cleared by an access from the S12X CPU. Otherwise, when using one of the
other masters (such as the XGATE) to clear this bit, the status flags and the address status registers
may not get updated correctly if a CPU access causes a violation in the same bus cycle.
Write-Protect Violation Flag — This flag is set if the current CPU access violation has occurred because of
an attempt to write to memory configured as read-only. The WPF bit is read-only; it will be automatically
updated when the next access violation is flagged with the AEF bit.
No-Execute Violation Flag — This bit is set if the current CPU access violation has occurred because of an
attempt to fetch code from memory configured as No-Execute. The NEXF bit is read-only; it will be
automatically updated when the next access violation is flagged with the AEF bit.
Supervisor State Flag — This bit is set if the current CPU access violation occurred while the CPU was in
supervisor state. This bit is cleared if the current CPU access violation occurred while the CPU was in user
state. The supervisor state flag is read-only; it will be automatically updated when the next CPU access
violation is flagged with the AEF bit.
If the AEF bit is set further violations are not captured into the MPU status registers. The status of the AEF
bit has no effect on the access restrictions, i.e. access restrictions for all masters are still enforced if the
AEF bit is set. Also, the non-maskable hardware interrupt for violating accesses coming from the S12X
CPU is generated regardless of the state of the AEF bit.
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
231
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