MC9S08QE128_08 Datasheet, PDF (23/50 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num C
Characteristic
Symbol
Min Typ¹ Max Unit
8
C
Total deviation of trimmed DCO output frequency over voltage
and temperature
9
C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δf_{dco_t}
Δf_{dco_t}
—
+ 0.5
-1.0
± 2 %f_dco
—
± 0.5
± 1 %f_dco
10 C _{FLL acquisition time} ³
t_Acquire
—
—
1
ms
Long term jitter of DCO output clock (averaged over 2-ms
11 C _{interval) 4}
C_Jitter
—
0.02
0.2 %f_dco
1 _{Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.}
2 _{The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.}
3 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a
given interval.
0.60%
0.40%
0.20%
0.00%
-40
-20
0
-0.20%
20
40
60
80
100
-0.40%
-0.60%
-0.80%
-1.00%
VDD
Figure 15. Deviation of DCO Output Across Temperature at V_DD = 3.0 V
Freescale Semiconductor
MC9S08QE128 Series Data Sheet, Rev. 7
120
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