MC9S08QE128_08 Datasheet, PDF (14/50 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Electrical Characteristics
For most applications, P_I/O << P_int and can be neglected. An approximate relationship between P_D and T_J (if P_I/O is neglected)
is:
P_D = K ÷ (T_J + 273°C)
Solving Equation 1 and Equation 2 for K gives:
Eqn. 2
K = P_D × (T_A + 273°C) + θ_JA × (P_D)²
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P_D (at equilibrium)
for a known T_A. Using this value of K, the values of P_D and T_J can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of T_A.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Human
Body
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Machine Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Latch-up
Maximum input voltage limit
Symbol
Value
Unit
R1
1500
Ω
C
100
pF
—
3
R1
0
Ω
C
200
pF
—
3
– 2.5
V
7.5
V
Table 7. ESD and Latch-Up Protection Characteristics
No.
Rating¹
Symbol
Min
Max
Unit
1
Human body model (HBM)
V_HBM
± 2000
—
V
2
Machine model (MM)
V_MM
± 200
—
V
3
Charge device model (CDM)
V_CDM
± 500
—
V
4
Latch-up current at T_A = 85°C
I_LAT
± 100
—
mA
1 _{Parameter is achieved by design characterization on a small sample size from typical devices}
under typical conditions unless otherwise noted.
MC9S08QE128 Series Data Sheet, Rev. 7
14
Freescale Semiconductor