MC9328MX21S_08 Datasheet, PDF (22/88 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors 266 MHz

Specifications
VSYN
HSYN
OE
LD[17:0]
T1
T2
Line Y
Non-display region
T3
T4
Display region
Line 1
Line Y
T5
T6
XMAX
T7
HSYN
SCLK
OE
LD[15:0]
(0,1) (0,2)
(0,X-1)
Figure 12. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Table 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
Minimum
Value
Unit
T1
End of OE to beginning of VSYN
T5+T6+T7-1
(VWAIT1·T2)+T5+T6+T7-1
Ts
T2
HSYN period
–
XMAX+T5+T6+T7
Ts
T3
VSYN pulse width
T2
VWIDTH·T2
Ts
T4
End of VSYN to beginning of OE
1
(VWAIT2·T2)+1
Ts
T5
HSYN pulse width
1
HWIDTH+1
Ts
T6
End of HSYN to beginning to OE
3
HWAIT2+3
Ts
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
Note:
• Ts is the SCLK period.
• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 12, all 3 signals are active low.
• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 12, SCLK is
always active.
• XMAX is defined in number of pixels in one line.
MC9328MX21S Technical Data, Rev. 1.3
22
Freescale Semiconductor