MC9328MX21S_08 Datasheet, PDF (15/88 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors 266 MHz

Specifications
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz)
with an operating supply voltage from V_{DD min} to V_{DD max} under an operating temperature from T_L to T_H.
All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer
to the reference manual’s System Control Chapter for details on drive strength settings.
Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also
known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock
(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and
other signals required to meet 133 MHz timing.
The values shown in Table 8 apply over the recommended operating temperature range. Care must be
taken to minimize parasitic capacitance of associated printed circuit board traces.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133 MHz Operation
Drive Strength Setting (DSCR2–DSCR12)
000: 3.5 mA
001: 4.5 mA
011: 5.5 mA
111: 6.5 mA
Maximum I/O Loading at 1.8 V
9 pF
12 pF
15 pF
19 pF
Maximum I/O Loading at 3.0 V
12 pF
16 pF
21 pF
26 pF
Table 9. 32k/26M Oscillator Signal Timing
Parameter
EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL
EXTAL32k input jitter (peak to peak) for MCUPLL only
EXTAL32k startup time
Minimum
–
–
800
RMS
5
5
–
Maximum Unit
20
ns
100
ns
–
ms
Table 10. CLKO Rise/Fall Time (at 30pF Loaded)
Rise Time
Fall Time
Best Case
0.80
0.74
Typical
1.00
1.08
Worst Case
1.40
1.67
Units
ns
ns
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
15