MC9328MX21S_08 Datasheet, PDF (10/88 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors 266 MHz

Signal Descriptions
Table 2. i.MX21S Signal Descriptions (Continued)
Signal Name
USBH1_RXDP
USBH1_RXDM
USBH1_TXDP
USBH1_TXDM
USBH1_RXDAT
USBH1_OE
USBH1_FS
USBH_ON
USBG_SCL
USBG_SDA
USBG_TXR_INT
SD1_CMD
SD1_CLK
SD1_D[3:0]
SD2_CMD
SD2_CLK
SD2_D[3:0]
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
UART3_RXD
UART3_TXD
UART3_RTS
UART3_CTS
UART4_RXD
UART4_TXD
UART4_RTS
Function/Notes
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USB OTG I²C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8.
USB OTG I²C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7.
USB OTG transceiver interrupt input. Multiplexed with USBG_FS.
Secure Digital Interface
SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-
up, via the Pull-up enable register, a 4.7k–69k external pull-up resistor must be added.
SD Output Clock.
SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 50k–69k external pull-up resistor must be added.
SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1.
SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals
from SLCDC1.
UARTs – IrDA/Auto-Bauding
(Note: UART2 is not used in the MC9328MX21S)
Receive Data input signal
Transmit Data output signal
Request to Send input signal
Clear to Send output signal
Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI.
Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI.
Request to Send input signal
Clear to Send output signal
Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP.
Transmit Data output signal which is multiplexed with USBH1_TXDM.
Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP.
MC9328MX21S Technical Data, Rev. 1.3
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Freescale Semiconductor