AR4100 Datasheet, PDF (22/29 Pages) Freescale Semiconductor, Inc – Low power modes consuming as little as 5 μA of current

AR4100 System in Package 802.11n– General Availability Data Sheet
Pin Assignments and Descriptions
Table 5-3 Signal-to-Pin Relationships and Descriptions
Signal Name
Pin
Type
Reset
State
I/O Pad Supply
Domain
Description
Digital Control
HMODE0
T7
I
X
VDDIO
WiFi host mode select, see design guide for
configuration details, floating input must be
tied high or low.
HMODE1
R7
I
X
VDDIO
WiFi host mode select, see design guide for
configuration details, floating input must be
CHIP_PWD_L
T11
m _{Host Interface (SPI Mode)}
SPI_MOSI
D1
o _{SPI_CLK}
J1
.c ^SPI_MISO
H1
SPI_INT
G1
SPI_CS
E1
le ^{Master SPI Flash Interface}
SPIM_CLK
P2
SPIM_CS_N
M2
a _{SPIM_MISO}
N2
SPIM_MOSI
R2
c _{RF Port}
s _{WIFI_RF}
T4
System Test
e _{DEBUG_}
T10
UART_RXD
e _{DEBUG_}
T6
UART_TXD
r _TMS
T8
.f _TCK
T9
www ^TDI
R9
tied high or low.
I, PD Low HOST_POWER WLAN Power Down
0 Power down
1 WLAN awake
I/O
PU HOST_POWER SPI data Input
I
X HOST_POWER SPI clock must be driven.
I/O
PU HOST_POWER SPI data output
I/O
PU HOST_POWER SPI interrupt
I/O
PU HOST_POWER SPI chip select
I/O
X
I/O High
I/O High
I/O
X
VDDIO
VDDIO
VDDIO
VDDIO
Master SPI clock for SPI flash interface
Master SPI chip select for SPI flash interface
Master SPI data input for SPI flash interface
Master SPI data output for SPI flash interface
A_I/O N/A
N/A
RF antenna port
I/O Low
O
High
I, PU High
I, PU High
I, PU High
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
Reconfigured after software download as
debugging UART RXD
Reconfigured after software download as
debugging UART TXD
WiFi JTAG TMS
Used with debugging only
WiFi JTAG TCK
Used with debugging only
WiFi JTAG TDI
Used with debugging only
MKG-16487 Ver. 5.0
22
Qualcomm Atheros, Inc.
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