AR4100 Datasheet, PDF (13/29 Pages) Freescale Semiconductor, Inc – Low power modes consuming as little as 5 μA of current

AR4100 System in Package 802.11n– General Availability Data Sheet
WiFi Functional Description
3.5 System Clocking (RTC Block)
The AR4100 has an RTC block which controls the clocks and power going to other internal
modules. Its inputs consist of sleep requests from these modules and its outputs consists of clock
enable and power signals which are used to gate the clocks going to these modules. The RTC block
also manages resets going to other modules with the device. The AR4100’s clocking is grouped
into two types: high-speed and low-speed.
3.5.1 High Speed Clocking
The reference clock source drives the PLL and RF synthesizer within the AR4100. To minimize
power consumption, the reference clock source is powered off in the SLEEP, HOST_OFF, and
OFF states.
m _{When exiting SLEEP state, the AR4100 waits in WAKEUP state for a programmable duration.}
o _{3.5.2 Low-Speed Clocking}
.c ^{The AR4100 has eliminated the need for an external sleep clock source thereby reducing system}
cost. Instead, an internal ring oscillator is used to generate a low frequency sleep clock. It is also
used to run the state machines and counters inside the AR4100’s power control module (PCM).
le ^{The PCM controls all power and isolation control signals for the entire chip.}
The AR4100 has an internal calibration module which produces a 32.768 KHz output with
a _{minimal variation. For this, it uses the reference clock source as the golden clock. As a result, the}
calibration module adjusts for process and temperature variations in the ring oscillator when the
c _{system is in ON state.}
s _{3.5.3 Interface Clock}
e _{The host interface clock is another clock domain for the AR4100. This clock comes from the GSPI}
e _{host and is completely independent from the other internal clocks.}
.fr ^{3.6 MAC/BB/RF Block}
The AR4100 Wireless MAC consists of five major blocks:
 Host interface unit (HIU) for bridging to the AHB for VMC data accesses and APB for
register accesses
w _{ Ten queue control units (QCU) for transferring Tx data}
 Ten DCF control units (DCU) for managing channel access
w_{ Protocol control unit (PCU) for interfacing to baseband}
w^{ DMA receive unit (DRU) for transferring Rx data}
3.7 Baseband Block
The AR4100 baseband module (BB) is the physical layer controller for the 802.11 b/g/n air
interface. It is responsible for modulating data packets in the transmit direction, and detecting and
demodulating data packets in the receive direction. It has a direct control interface to the radio to
enable hardware to adjust analog gains and modes dynamically.
MKG-16487 Ver. 5.0
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Qualcomm Atheros, Inc.
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