AR4100 Datasheet, PDF (16/29 Pages) Freescale Semiconductor, Inc – Low power modes consuming as little as 5 μA of current

AR4100 System in Package 802.11n– General Availability Data Sheet
Electrical Characteristics
Figure 4-1 and Figure 4-2 show the recommended power up/down and reset sequences for the
AR4100 using external 3.3 V and 1.8 V supplies.
om _{Figure 4-1 Power Up/Power Down Timing}
escale.c _{Figure 4-2 Reset and Power Cycle Timing}
e _Where:
r _{ VBAT = VBATTERY_42}
.f _{ I/O = VDDIO, HOST_POWER}
Table 4-5 Reset and Power Cycle Timing
w Variable
T_a
w _Tb
w^Tc
Description
Min (μsec) Max (μsec)
Time between VBAT, VDD33 and I/O supplies becoming valid and 1.8 V
0
—
supply becoming valid¹
Time between the 1.8 V becoming valid and the CHIP_PWD_L deassertion
0
500
Time between the CHIP_PWD_L assertion and the 1.8 VG supply becoming
0
—
invalid
T_d
Time between the 1.8 V supply becoming invalid and VBAT, VDD33 and I/O
N/A²
—
supplies becoming invalid
T_e
Length of the CHIP_PWDP_L pulse
5
—
1. “Supply becoming valid” denotes that the voltage level has reached 90%
2. No strict requirements. This parameter can also be negative.
MKG-16487 Ver. 5.0
16
Qualcomm Atheros, Inc.
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