AR4100 Datasheet, PDF (12/29 Pages) Freescale Semiconductor, Inc – Low power modes consuming as little as 5 μA of current

AR4100 System in Package 802.11n– General Availability Data Sheet
Figure 3-1 depicts the state transition diagram.
WiFi Functional Description
le.com _{Figure 3-1 AR4100 Power States}
a _{Table 3-1 Power Management States}
c _State
s _OFF
ee _{HOST_OFF}
www.fr ^SLEEP
Description
CHIP_PWD_L pin assertion immediately brings the chip to this state.
Sleep clock is disabled.
No state is preserved.
Host power LDO turned OFF.
WLAN is turned OFF.
Only the host interface is powered on - the rest of the chip is power gated OFF.
The host instructs the AR4100 to transition to WAKEUP by writing a register in the host interface
domain.
Embedded CPU and WLAN do not retain state (separate entry).
This state can be bypassed by asserting FORCE_HOST_ON_L during CHIP_PWD_L
deassertion.
Only the sleep clock is operating.
The reference clock is disabled.
Any wakeup events (MAC, host, LF-Timer) will force a transition from this state to the WAKEUP
state.
All internal states are maintained.
WAKEUP
The system transitions from sleep states to ON.
ON
The high speed clock is operational and sent to each block enabled by the clock control register.
Lower level clock gating is implemented at the block level, including the CPU, which can be
gated OFF using the WAITI instruction while the system is ON. No CPU, host, and WLAN
activities will transition to sleep states.
MKG-16487 Ver. 5.0
12
Qualcomm Atheros, Inc.
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