MRF6V14300HR3 Datasheet, PDF (2/10 Pages) Freescale Semiconductor, Inc – RF Power Field Effect Transistors

Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22 - A114)
1C (Minimum)
Machine Model (per EIA/JESD22 - A115)
A (Minimum)
Charge Device Model (per JESD22 - C101)
IV (Minimum)
Table 4. Electrical Characteristics (T_C = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Off Characteristics
Gate- Source Leakage Current
(V_GS = 5 Vdc, V_DS = 0 Vdc)
Drain- Source Breakdown Voltage
(V_GS = 0 Vdc, I_D = 100 mA)
Zero Gate Voltage Drain Leakage Current
(V_DS = 50 Vdc, V_GS = 0 Vdc)
Zero Gate Voltage Drain Leakage Current
(V_DS = 90 Vdc, V_GS = 0 Vdc)
I_GSS
—
—
10
μAdc
V_(BR)DSS
100
—
—
Vdc
I_DSS
—
—
50
μAdc
I_DSS
—
—
2.5
mA
On Characteristics
Gate Threshold Voltage
(V_DS = 10 Vdc, I_D = 662 μAdc)
Gate Quiescent Voltage
(V_DD = 50 Vdc, I_D = 150 mAdc, Measured in Functional Test)
Drain- Source On - Voltage
(V_GS = 10 Vdc, I_D = 1.63 Adc)
Dynamic Characteristics ⁽¹⁾
Reverse Transfer Capacitance
(V_DS = 50 Vdc ± 30 mV(rms)ac @ 1 MHz, V_GS = 0 Vdc)
Output Capacitance
(V_DS = 50 Vdc ± 30 mV(rms)ac @ 1 MHz, V_GS = 0 Vdc)
Input Capacitance
(V_DS = 50 Vdc, V_GS = 0 Vdc ± 30 mV(rms)ac @ 1 MHz)
V_GS(th)
0.9
1.6
2.4
Vdc
V_GS(Q)
1.5
2.4
3
Vdc
V_DS(on)
—
0.26
—
Vdc
C_rss
—
0.6
—
pF
C_oss
—
350
—
pF
C_iss
—
330
—
pF
Functional Tests (In Freescale Test Fixture, 50 ohm system) V_DD = 50 Vdc, I_DQ = 150 mA, P_out = 330 W Peak (39.6 W Avg.), f = 1400 MHz,
Pulsed, 300 μsec Pulse Width, 12% Duty Cycle
Power Gain
Drain Efficiency
G_ps
16.5
18
19.5
dB
η_D
59⁽²⁾
60.5⁽²⁾
—
%
Input Return Loss
IRL
—
- 12
-9
dB
Pulsed RF Performance (In Freescale Application Test Fixture, 50 ohm system) V_DD = 50 Vdc, I_DQ = 150 mA, P_out = 330 W Peak
(39.6 W Avg.), f1 = 1200 MHz, f2 = 1300 MHz and f3 = 1400 MHz, Pulsed, 300 μsec Pulse Width, 12% Duty Cycle, t_r = 50 ns
Relative Insertion Phase
|ΔΦ|
—
10
—
°
Gain Flatness
Pulse Amplitude Droop
Harmonic 2nd and 3rd
G_F
—
0.5
—
dB
D_rp
—
0.3
—
dB
H2 & H3
—
- 20
—
dBc
Spurious Response
—
- 65
—
dBc
Load Mismatch Stability
(VSWR = 3:1 at all Phase Angles)
VSWR - S
All Spurs Below - 60 dBc
Load Mismatch Tolerance
(VSWR = 5:1 at all Phase Angles)
VSWR - T
No Degradation in Output Power
1. Part internally matched both on input and output.
2.
Drain
efficiency
is
calculated
by:
h_D
+
100
V_DD
P_out
I_peak
where: I_peak = (I_AVG - I_DQ) / Duty Cycle (%) + I_DQ.
MRF6V14300HR3 MRF6V14300HSR3
2
RF Device Data
Freescale Semiconductor