MC9S08PT16 Datasheet, PDF (14/33 Pages) Freescale Semiconductor, Inc – MC9S08PT16

Switching specifications
Table 5. Control timing (continued)
Num C
Rating
3
D External reset pulse width²
Symbol
t_extrst
4
D Reset low drive
5
D BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
t_rstdrv
t_MSSU
6
D BKGD/MS hold time after issuing background
t_MSH
debug force reset to enter user or BDM modes³
7
D
IRQ pulse width
Asynchronous
t_ILIH
path²
D
Synchronous path⁴
t_IHIL
8
D Keyboard interrupt pulse Asynchronous
t_ILIH
width
path²
D
Synchronous path
t_IHIL
9
C
Port rise and fall time -
—
t_Rise
C
Normal drive strength
(HDRVE_PTXx = 0) (load
t_Fall
= 50 pF)⁵
C Port rise and fall time -
—
t_Rise
C
Extreme high drive
strength (HDRVE_PTXx =
t_Fall
1) (load = 50 pF)⁵

Min
1.5 ×
t_{Self_rese}^_t
34 × t_cyc
500
100
100 _
1.5 × t_cyc
100 _
1.5 × t_cyc
—
—
—
—
Typical¹
—
—
—
—
—
—
—
—
10.2
9.5
5.4
4.6

Max
Unit
—
ns
—
ns
—
ns

—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
1. Typical values are based on characterization data at V_DD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t_MSH after
V_DD rises above V_LVD.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchroniza_ tion circu_itry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% V_DD and 80% V_DD levels. Temperature range -40 °C to 105 °C.
RESET PIN
t_extrst
Figure 5. Reset timing
t_IHIL
KBIPx
IRQ/KBIPx
t_ILIH
Figure 6. IRQ/KBIPx timing
MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012.
14
Freescale Semiconductor, Inc.