56F8365_07 Datasheet, PDF (133/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Introduction
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F8300 Peripheral User Manual.
8.2 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and
GPIOx_PER registers change from port to port. Tables 4-29 through 4-34 define the actual reset values of
these registers.
8.3 Configuration
There are six GPIO ports defined on the 56F8365/56F8165. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8365 GPIO Ports Configuration
GPIO Port
Port
Width
A
14
B
8
C
11
D
13
E
14
Available
Pins in
56F8365
6
5
11
Peripheral Function
6 pins - EMI Address pins - Can only be used as GPIO
8 pins - EMI Address pins - Not available in this package
5 pins - EMI Address pins - Can only be used as GPIO
3 pins - EMI Address pins - Not available in this package
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense
11
2 pins - EMI CSn
4 pins - EMI CSn - Can only be used as GPIO
2 pins - SCI1
2 pins - EMI CSn - Not available in this package
3 pins -PWMB current sense
12
2 pins - SCI0
2 pins - EMI Address pins - Not available in this package
4 pins - SPI0
2 pins - TMRC
4 pins - TMRD
Reset Function
EMI Address
N/A
GPIO
N/A
DEC1 / TMRB
DEC0 / TMRA
PWMA current
sense
EMI Chip Selects
EMI Chip Selects
SCI1
N/A
PWMB current
sense
SCI0
N/A
SPI0
TMRC
TMRD
56F8365 Technical Data, Rev. 7
Freescale Semiconductor
133
Preliminary