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33797 Datasheet, PDF (13/34 Pages) Freescale Semiconductor, Inc – Four Channel Squib Driver IC | |||
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ⤠VDD ⤠5.25 V; 7.0 V ⤠VVFIRE_XX ⤠35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2
= VDD; RR_LIMIT_X = 10 k⦠±1%, RR_DIAG = 10 k⦠±1%, -40°C ⤠TA ⤠+85°C, GND = 0 unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SERIAL INTERFACE
CLK Cycle Time (1/FCLK) (18)
CLK High Time (18)
VCLK > VDD x 70%
CLK Low Time (18)
VCLK < VDD x 20%
Clock Rise Time (18)
VCLK = 20% VDD to 70% VDD, CLOAD = 100 pF
Clock Fall Time (18)
VCLK = 70% VDD to 20% VDD, CLOAD = 100 pF
Data Out Rise Time (19)
VDO = 20% VDD to 70% VDD, CLOAD = 100 pF
Data Out Fall Time (19)
VDO = 70% VDD to 20% VDD, CLOAD = 100 pF
Chip Select Setup Time (19)
CSB â Before CLK â
Chip Select Hold Time (19)
CLK â Before CSB â
Data In Setup Time (19)
D1 Valid Before CLK
tCYC
200
â
tHI
34
â
tLO
34
â
tRISE
â
â
tFALL
â
â
tR
â
â
tF
â
â
tLEAD
62
â
tLAG
62
â
tSU
30
â
â
ns
ns
â
ns
â
ns
20
ns
20
ns
20
ns
20
ns
â
ns
â
ns
â
Data In Hold Time (19)
D1 Hold Time After CLK â
Data Out Access Time (19)
CSB to D0 Valid
tH
ns
30
â
â
tA
ns
â
â
62
Data Out Disable Time (19)
CSB â to D0 HI-Z
Data Out Valid Time (19)
CLK â to D0 Valid, CLOAD = 100 pF
Data Out Hold Time (19)
D0 held After CLK â
tDIS
ns
â
â
62
tV
ns
â
â
75
tHO
0.0
â
ns
â
Diagnostic Delay Time (Between Two Successive Commands)
tDIAG
2.5
â
â
µs
Notes
18 Determined by Design
19 Guaranteed by Characterization
Analog Integrated Circuit Device Data
Freescale Semiconductor
33797
13
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