33982B_09 Datasheet, PDF (10/36 Pages) Freescale Semiconductor, Inc – Single Intelligent High-current Self-protected Silicon High Side Switch (2.0 mΩ)

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ V_DD ≤ 5.5 V, 6.0 V ≤ V_PWR ≤ 27 V, -40°C ≤ T_A ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (CONTINUED)
Output Negative Clamp Voltage
0.5 A < I_HS < 2.0 A, Output OFF
Over-temperature Shutdown⁽¹³⁾
Over-temperature Shutdown Hysteresis⁽¹³⁾
V_CL
V
- 20
–
-15
T_SD
160
175
190
°C
T_SD(HYS)
5.0
–
20
°C
CONTROL INTERFACE
Input Logic High-voltage⁽¹⁴⁾
Input Logic Low-voltage⁽¹⁴⁾
Input Logic Voltage Hysteresis⁽¹⁵⁾
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
SO, FS Tri-state Capacitance⁽¹⁶⁾
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance⁽¹⁶⁾
WAKE Input Clamp Voltage⁽¹⁷⁾
I_CL(WAKE) < 2.5 mA
V_IH
0.7 x V_DD
–
V_IL
–
–
V_IN(HYS)
100
600
I_DWN
5.0
–
V_RST
4.5
5.0
C_SO
–
–
R_DWN
100
200
C_IN
–
4.0
V_CL(WAKE)
7.0
–
–
V
0.2 x
V
V_DD
1200
mV
20
μA
5.5
V
20
pF
400
kΩ
12
pF
V
14
WAKE Input Forward Voltage
I_CL(WAKE) = -2.5 mA
V_F(WAKE)
- 2.0
V
–
-0.3
SO High-state Output Voltage
I_OH = 1.0 mA
V_SOH
0.8 x V_DD
–
V
–
FS, SO Low-state Output Voltage
I_OL = -1.6 mA
V_SOL
V
–
0.2
0.4
SO Tri-state Leakage Current
CS > 0.7 x V_DD
Input Logic Pull-up Current ⁽¹⁸⁾
CS, V_IN > 0.7 x V_DD
I_SO(LEAK)
-5.0
I_UP
5.0
μA
0.0
5.0
μA
–
20
FSI Input Pin External Pull-down Resistance
FSI Disabled, HS Indeterminate
FSI Enabled, HS OFF
FSI Enabled, HS ON
R_FS
kΩ
R_FSDIS
–
0.0
1.0
R_FSOFF
6.0
10
14
R_FSON
30
–
–
Notes
13. Guaranteed by process monitoring. Not production tested.
14. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage reference to V_PWR.
15. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
16. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
17. The current must be limited by a series resistance when using voltages > 7.0 V.
18. Pull-up current is with CS OPEN. CS has an active internal pull-up to V_DD.
33982
10
Analog Integrated Circuit Device Data
Freescale Semiconductor