FAMP0417CAX-W70E Datasheet, PDF (6/12 Pages) FIDELIX – 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FMP0417CAx-W70E
CMOS LPRAM
AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : T_A=-25 to 85’C)
Parameter List
Read
Write
Page
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
/UB, /LB Access Time
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Page Mode Cycle Time
Page Mode Address Access Time
Maximum Cycle Time
/CS High Pulse Width¹⁾
Symbol
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
tPC
tPAA
tMRC
tCP
70ns
Min
Max
70
20K
-
70
-
70
-
25
-
70
10
-
10
-
5
-
0
5
0
5
0
5
5
-
70
20K
60
-
0
-
60
-
60
-
50
-
0
-
0
5
20
-
0
-
5
-
25
-
-
25
-
20k
10
-
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
Revision 0.0
Feb. 2008