FAMP0417CAX-W70E Datasheet, PDF (10/12 Pages) FIDELIX – 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FMP0417CAx-W70E
CMOS LPRAM
PAGE WRITE CYCLE (Address controlled, /ZZ=VIH)
A0~A3
tMRC
tWC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
A4~A17
/CS
/UB, /LB
/WE
tAS(3)
Data in
Data Out
High-Z
tWHZ
Data Undefined
tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW ^{tDH tDW tDH}
Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid
High-Z
tOW
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
6. In case page address is over 3ns, write to the invalid address can occur.
10
Revision 0.0
Feb. 2008