M21050_17 Datasheet, PDF (65/70 Pages) M/A-COM Technology Solutions, Inc. – Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)

Product Specifications
Typically, the preferred solution for trace length matching in differential pairs is to use a serpentine pattern for the
shorter signal as shown in Figure 3-10. Using a serpentine pattern for length matching will minimize the differential
impedance discontinuity while making both trace lengths equal.
Figure 3-10. Trace Length Matching Using Serpentine Pattern
The loop length matching method shown in Figure 3-11 will match the trace lengths of a differential pair, but will
create a large impedance discontinuity in the transmission line, which could result in higher jitter on the signal and/
or a greater sensitivity to noise for the differential pair.
Figure 3-11. Loop Length Matching for Differential Traces
When using capacitors to AC couple the input, care should be taken to minimize the pattern-dependant jitter (PD_J)
associated with the low-frequency cutoff of the coupling network. When NRZ data containing long strings of 1s or
0s is applied to a high-pass filter, a voltage droop occurs. This voltage droop causes PD_J in much the same fashion
as inter-symbol interference (ISI) is generated from dispersion effects of long lengths of backplane material.
If needed, use 0.1 µF capacitors to AC-couple the high-speed output signals, and the reference clock inputs. The
high-speed data input signals must be AC-coupled.
On the Evaluation Module (EVM), we have tied DVdd_I/O and AVdd_I/O together to minimize the number of power
supply jacks. They are kept separate on-device to give the flexibility to the system designers to supply a different
voltage level for each. For instance, an FPGA can supply DVdd_I/O, while a lower AVdd_I/O can be used to mini-
mize power dissipation. On the EVM, we have also tied DVdd_Core and AVdd_Core together to minimize the
number of power supply jacks. They are kept separate on-device to provide more isolation, however, if the system
board plane is properly decoupled, they can be tied together.
No inductive filtering on the system board is necessary between different power supplies of the device. It is up to
the system designer to determine if this needs to be considered for supplies that are coming from other parts of the
system board (such as switching regulators or ASICs).
An inductor should not be used at the VddT pins. These pins were made available to create a low AC impedance,
such that the 50Ω on-device termination impedances see a common AC ground. This assures both common-mode
and differential termination. Note that a low AC impedance can also be created by tying the VddT pins to the
AVdd_Core plane, thus saving on the number of external capacitors. VddT is not really a supply plane on-device,
it is simply the point to which the 50Ω input impedances are tied.
Power planes should be decoupled to ground planes using thin dielectric layers, to increase capacitance (prefera-
bly 2-4 mils). Reference ground layers should be used on both sides of inner layer routing planes, with controlled
impedance. The total board thickness should meet the standard drill holes to board thickness ratio of 1:12 or 1:14.
21050-DSH-001-F
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