M21050_17 Datasheet, PDF (54/70 Pages) M/A-COM Technology Solutions, Inc. – Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)

M21050 Data Sheet
Table 3-6. PCML (Positive Current Mode Logic) Output Electrical Specifications
Symbol
Parameter
Notes
Minimum
Typical
Maximum
DR_OUT Output signal data-rates
1
t_r/t_f
Rise/Fall time (20-80%) for all levels
1
V_OH
Low Swing: output logic high (single-ended)
1
V_OL
Low Swing: output logic low (single-ended)
1
V_OD
Low Swing: differential swing
1, 2
V_OH
Medium Swing: output logic high (single-ended)
1
V_OL
Medium Swing: output logic low (single-ended)
1
V_OD
Medium Swing: differential swing
1, 2
V_OH
High Swing: output logic high (single-ended)
1
V_OL
High Swing: output logic low (single-ended)
1
V_OD
High Swing: differential swing
1, 2
V_OH
InfiniBand Swing: output logic high (single-ended)
1
V_OL
InfiniBand Swing: output logic low (single-ended)
1
V_OD
InfiniBand Swing: differential swing
1, 2
R_OUT
Output termination to AVdd_I/O
1
S₂₂
Output return loss (40 MHz to 2.5 GHz)
1
S₂₂
Output return loss (2.5 GHz to 5 GHz)
1
Notes:
1. Specified at recommended operating conditions – see Table 3-2.
2. Example 1200 mV _P-P differential = 600 mV _P-P for each single-ended terminal.
3. All output swings defined with pre-emphasis off.
1
—
AVdd_I/O – 65
AVdd_I/O – 370
400
AVdd_I/O – 85
AVdd_I/O – 600
700
AVdd_I/O – 100
AVdd_I/O – 770
1000
AVdd_I/O – 120
AVdd_I/O – 1000
1050
45
—
—
—
100
—
—
500
—
—
850
—
—
1100
—
—
1500
50
–15.0
–5.0
3.2
130
AVdd_I/O
AVdd_I/O – 240
650
AVdd_I/O
AVdd_I/O – 400
1100
AVdd_I/O
AVdd_I/O – 500
1200
AVdd_I/O
AVdd_I/O – 600
1900
65
—
—
Units
Gbps
ps
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Ω
dB
dB
Table 3-7. Input Equalization Performance Specifications
Symbol
Parameter
Notes Minimum Typical Maximum Units
DR_IN
Input signal data-rates
1
1
—
3.2
Gbps
—
Maximum error-free distance at 3.1875 Gbps
1, 2, 3, 5
—
—
60
in
—
Maximum error-free distance at 2.125 Gbps
1, 2, 3, 5
—
—
72
in
Notes:
1. Specified at recommended operating conditions – see Table 3-2.
2. Performance measured on standard FR4 backplane such as standards provided by TYCO for 10GE XAUI.
3. Measured with PCML driver WITHOUT output pre-emphasis at a minimum launch voltage of 1 Vpp output swing at beginning of line.
4. Combined input equalization + output pre-emphasis performance will be better than individual performance, but less than the sum of the two lengths.
5. Default setting optimized for driving 10 - 46 in of PCB trace length. Equalizer can be configured for longer reach using two-wire interface.
6. For applications where input equalization setting cannot be dynamically re-configured, adaptive input equalization may be enabled. See Section 1.1.10 for additional details.
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21050-DSH-001-F
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