FAN6210 Datasheet, PDF (8/11 Pages) Fairchild Semiconductor – Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter

SIN
SOUT
300ns
XP
XN
50ns
300ns
Heavy load condition
Programmable delay
700ns
100ns
50ns
700ns
50ns
300ns
300ns
Programmable delay
50ns
300ns
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
SIN
SOUT
300ns
XP
XN
50ns
300ns
Light load condition
Programmable delay
700ns
100ns
50ns
700ns
50ns
300ns
300ns
Programmable delay
50ns
300ns
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
Figure 16. Timing Diagram
t _{DLY_XP} (ns)
350
300
Under-Voltage Lockout (UVLO)
The power-on and -off threshold of FAN6210 are fixed
at 10V and 8V, respectively. The VDD pin can be
connected with the power source of the PWM controller.
250
200
150
100
5 7.5 10 12.5 15 17.5 20 22.5 25
R_RDLY (kΩ)
Figure 17. Programmable Delay with Resistor
VDD Pin Over-Voltage Protection
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage exceeds the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tOVP, FAN6210 stops operation.
Green-Mode Operation
To improve light-load efficiency, green-mode operation
is employed, which disables the SR turn-on trigger
signal, minimizing gate drive power consumption at
light-load condition. Green mode is enabled when the
duty cycle of SIN is smaller than 10%.
© 2009 Fairchild Semiconductor Corporation
FAN6210 Rev. 1.0.1
8
www.fairchildsemi.com