FAN6210 Datasheet, PDF (7/11 Pages) Fairchild Semiconductor – Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter

Function Description
Figure 13 and Figure 14 show the simplified circuit
diagram of dual-forward converter and its key
waveforms. Switches Q1 and Q2 are turned on and off
together. Once Q1 and Q2 are turned on, input voltage
is applied across the transformer primary side and
power is delivered to the secondary side through the
transformer, powering diode D1. During this time, the
magnetizing current linearly increases. When Q1 and
Q2 are turned off, the magnetizing current of the
transformer forces the reset diodes (DR1 and DR2) and
negative input voltage is applied across the transformer
primary side. During this time, magnetizing current
linearly decreases to zero and the secondary-side
inductor current freewheels through diode D2. When
synchronous rectifiers SR1 and SR2 are used instead
of diodes D1 and D2, it is important to have proper
timing between drive signals for SR1 and SR2.
Q1
+
V_IN
V_D
D_R1
-
Q2
D_R2
L_m
I_m
+
Vx
-
L
V_o
SR2
I_L
D₁
D₂
SR1
Figure 13. Simplified Circuit Diagram of
Dual-Forward Converter
Vgs
Q1,Q2
Vx
V_in
V_D
V_in
I_M
I_L
I_D1
I_D2
Figure 14. Key Waveforms of Dual-Forward
Converter
Figure 15 shows the typical application circuit of
FAN6210. SIN is the gate drive output of the PWM
controller. SOUT is obtained from SIN by adding a
delay, which is used to drive two switches Q1 and Q2.
The value of the DET resistor is recommended as 10kΩ
and DB is used to block high voltage on winding. The
breakdown voltage of Zener diode DZ is typically 5~6V
to protect the DET pin from over voltage.
VIN +
From PWM
controller
Q1
Drv
FAN6210
1 _XP
8
GND
2 _{XN SOUT} 7
3 _{SIN VDD} 6
4 _{RDLY DET} 5
D_B
Q2
D_z
Drv
-
SN of FSR660/630
SP of FSR660/630
Figure 15. Typical Application Circuit
Figure 16 shows the timing diagrams for heavy-load
and light-load conditions.
The switching operation of the secondary SR
MOSFETs is determined by the SN and SP signals.
FSR660/630 turns on SR MOSFETs at the rising edge
of the XP signal, while it turns off SR MOSFETs at the
rising edge of XN. Within one switching cycle, XP and
XN are obtained two times, respectively.
The XN signal has a 300ns pulse-width and is triggered
by the rising edge and falling edge of the SIN signal
after a short time delay (tPD_XN).
XP signal has a 700ns pulse-width and is triggered by
the rising edge of the SOUT signal after an adjustable
time delay (tDLY_XP) and by the falling edge of the DET
signal. The relation between the delay resistor (RDELAY)
and the delay time is shown in Figure 17. The triggering
of the XP signal by DET is prohibited while the XN
signal is HIGH. Therefore, the XP signal is not triggered
at the falling edge of the DET signal and is delayed until
the XN signal drops to zero at heavy-load condition. At
light-load condition, the DET falling edge comes after
the XN signal drops to zero and the XP signal is
triggered at the falling edge of the DET signal after a
short time delay (tPD_DET).
© 2009 Fairchild Semiconductor Corporation
FAN6210 Rev. 1.0.1
7
www.fairchildsemi.com