FAN6210 Datasheet, PDF (5/11 Pages) Fairchild Semiconductor – Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter

Electrical Characteristics
VDD=20V, TA=25℃, unless otherwise specified.
Symbol
Parameter
Conditions Min. Typ. Max. Units
VDD Section
VDD
VDD-ON
VTH-OFF
VDD-OVP
VDD-OVP-HYS
tOVP
SIN Section
DC Supply Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
VDD Over-Voltage Protection (OVP)
Hysteresis voltage for VDD OVP
VDD OVP Debounce Time
7
24
V
9
10 11
V
7
8
9
V
23.0 25.5 28.0 V
0.3 0.8 1.3 V
250
μs
VSIN
Logic Input Voltage
tDLY_OUTH Delay Time Between SIN-HIGH and SOUT-HIGH
tDLY_OUTL Delay Time Between SIN-LOW and SOUT-LOW
tON_MAX SOUT Maximum On Time and Stop XP Pulse
DET Section
10.5
24.5 V
240 300 350 ns
75 100 150 ns
8.5 10.0 12.0 μs
VDET_H Detect Input Voltage to Send XP After SOUT Falling
VDET_L Voltage to Drive XP Signal After SOUT Falling
tPD_DET Delay Time to Send XP
XP XN Section
2.5 3.0 3.5 V
1.5 2.0 2.5 V
30 50 100 ns
tPLS_XN
tPLS_XP
tPD_XN
DPLS_OFF
High-Level Pulsewidth of XN Signal
High-Level Pulsewidth of XP Signal
Delay Time to Trigger XN by SIN Rising or Falling Edge
SIN Duty Ratio Shorter than DPLS_OFF Stop XP Pulse
250 300 350 ns
600 700 800 ns
25 50 75 ns
10
%
VXN
XN Signal Output Voltage Level
5.5
8.0 V
VXP
XP Signal Output Voltage Level
5.5
8.0 V
tR_XP
XP Rising Time
VDD = 15V;
CL = 100pF;
SOUT= 1V to 6V
30 ns
tF_XP
XP Falling Time
VDD = 15V;
CL = 100pF;
SOUT= 7V to 2V
30 ns
RDLY Section
VRDLY
RDLY Voltage
RRDLY=24kΩ
1.08 1.20 1.32 V
tDLY_XP
VZ
VOL
VOH
tR
Delay Time to Trigger XP by SOUT Rising Edge R_RDLY=24kΩ
280 340 400 ns
Output Voltage Maximum (Clamp)
VDD=25V
18.5 V
Output Voltage LOW
VDD=15V; IO = 50mA
1.5 V
Output Voltage HIGH
VDD=15V; IO = 50mA 10
V
SOUT Rising Time
VDD = 15V; CL = 5nF;
SOUT= 2V to 9V
30
70 120
ns
tF
SOUT Falling Time
VDD = 15V; CL = 5nF;
SOUT= 9V to 2V
30
50 100
ns
© 2009 Fairchild Semiconductor Corporation
FAN6210 Rev. 1.0.1
5
www.fairchildsemi.com