RFD16N05LSM9A Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – N-Channel Logic Level Power MOSFET 50V, 16A, 47 mΩ

RFD16N05LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
1.4
I_D = 16V
1.3 _{VDS = 15V}
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.1
1.0
0.9
0.8
0.7
0.6
0.5
4
5
6
7
V_GS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.5
I_D = 16A
PULSE DURATION = 80µs
2.0 DUTY CYCLE = 0.5% MAX.
1.5
1.0
0.5
0
-50
0
50
100
150
200
T_J, JUNCTION TEMPERATURE (^oC)
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.4
I_D = 250µA
1.3 VGS = VDS
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
0
50
100
150
200
T_J, JUNCTION TEMPERATURE (^oC)
FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION
TEMPERATURE
2000
1600
V_GS = 0V
f = 1MHz
1200
800
400
00
C_ISS
C_ISS = C_GS + C_GD
C_RSS = C_GD
C_OSS ≈ C_DS + C_GD
C_OSS
C_RSS
5
10
15
20
25
V_DS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
1.4
I_D = 250µA
1.2
1.0
0.8
0.6
0
-50
0
50
100
150
200
T_J, JUNCTION TEMPERATURE (^oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
50
10
R_L = 3.125Ω, V_GS = 5V
I_G(REF) = 0.60mA
PLATEAU VOLTAGES IN
37.5
DESCENDING ORDER:
8
V_DD = BV_DSS
V_DD
=
BV_DSS
V_DD
V_DD
=
=
0.75
0.50
BV_DSS
BV_DSS
V_DD
=
BV_DSS
V_DD = 0.25 BV_DSS
6
25
GATE
SOURCE
4
VOLTAGE
12.5
2
DRAIN SOURCE VOLTAGE
0
0
20 -I--G-----⁽--R-----E----F----⁾-
IG_(ACT)
t, TIME (µs)
80 -I--G-----⁽--R-----E----F-----⁾
IG_(ACT)
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
©2003 Fairchild Semiconductor Corporation
RFD16N05LSM Rev. C1