FDMS9410_F085 Datasheet, PDF (4/6 Pages) Fairchild Semiconductor – Distributed Power Architectures and VRM

Typical Characteristics
1000
100
200
100
If R = 0
t_AV = (L)(I_AS)/(1.3*RATED BV_DSS - V_DD)
If R ≠ 0
t_AV = (L/R)ln[(I_AS*R)/(1.3*RATED BV_DSS - V_DD) +1]
10
100us
OPERATION IN THIS
AREA MAY BE
1 ^{LIMITED BY rDS(on)}
SINGLE PULSE
TJ = MAX RATED
TC = 25^oC
0.1
1ms
10ms
100ms
0.1
1
10
100 200
V_DS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
10
STARTING T_J = 150^oC
STARTING TJ = 25^oC
1
0.001 0.01
0.1
1
10
100
t_AV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
200
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
150 ^{VDD = 5V}
100
T_J = 25^oC
50
T_J = 175^oC
T_J = -55^oC
0
2
3
4
5
6
7
8
V_GS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
200
100 ^{VGS = 0 V}
10
T_J = 175 ^oC
1
T_J = 25 ^oC
0.1
0.0 0.2 0.4 0.6 0.8 1.0 1.2
V_SD, BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Forward Diode Characteristics
200
150
100
80μs PULSE WIDTH
Tj=25^oC
V_GS
15V Top
10V
8V
7V
6V
5.5V
5V Bottom
50
5V
0
0
1
2
3
4
5
V_DS, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Saturation Characteristics
200
150
100
V_GS
15V Top
10V
8V
7V
6V
5.5V
5V Bottom
5V
50
80μs PULSE WIDTH
Tj=175^oC
0
0
1
2
3
4
5
V_DS, DRAIN TO SOURCE VOLTAGE (V)
Figure 10. Saturation Characteristics
©2015 Fairchild Semiconductor Corporation
4
FDMS9410_F085 Rev. 1.0
www.fairchildsemi.com