FDMS9410_F085 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Distributed Power Architectures and VRM

FDMS9410_F085
N-Channel PowerTrench^® MOSFET
40 V, 50 A, 4.4 mΩ
August 2015
Features
„ Typical R_DS(on) = 3.7 mΩ at V_GS = 10V, I_D = 50 A
„ Typical Q_g(tot) = 24 nC at V_GS = 10V, I_D = 50 A
„ UIS Capability
„ RoHS Compliant
„ Qualified to AEC Q101
Applications
„ Automotive Engine Control
„ PowerTrain Management
„ Solenoid and Motor Drivers
„ Electronic Steering
„ Integrated Starter/Alternator
„ Distributed Power Architectures and VRM
„ Primary Switch for 12V Systems
For current package drawing, please refer to the Fairchild web‐
site at https://www.fairchildsemi.com/package‐drawings/PQ/
PQFN08M.pdf
MOSFET Maximum Ratings T_J = 25°C unless otherwise noted.
Symbol
Parameter
V_DSS
V_GS
I_D
Drain-to-Source Voltage
Gate-to-Source Voltage
Drain Current - Continuous (V_GS=10) (Note 1)
Pulsed Drain Current
E_AS
Single Pulse Avalanche Energy
Power Dissipation
P_D
Derate Above 25^oC
T_J, T_STG Operating and Storage Temperature
R_θJC
Thermal Resistance, Junction to Case
R_θJA
Maximum Thermal Resistance, Junction to Ambient
T_C = 25°C
T_C = 25°C
(Note 2)
(Note 3)
Ratings
40
±20
50
See Figure 4
39
75
0.5
-55 to + 175
2
50
Units
V
V
A
mJ
W
W/^oC
o_C
o_C/W
o_C/W
Notes:
1: Current is limited by bondwire configuration.
2: Starting T_J = 25°C, L = 0.1mH, I_AS = 28A, V_DD = 40V during inductor charging and V_DD = 0V during time in avalanche.
3: R_θJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface
presented here is
of the
based
drain pins. R_θJC is
on mounting on a 1
guaranteed by design,
in² pad of 2oz copper.
while
R_θJAis
determined
by
the
board
design.
The maximum rating
Package Marking and Ordering Information
Device Marking
FDMS9410
Device
FDMS9410_F085
Package
Power56
Reel Size
13”
Tape Width
12mm
Quantity
3000units
©2015 Fairchild Semiconductor Corporation
1
FDMS9410_F085 Rev. 1.0
www.fairchildsemi.com