FAN50FC3 Datasheet, PDF (4/21 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller

Pin Definitions (Continued)
14
15
16
17 to 19
20 to 22
23
24 to 31
32
GND
OD#
VOSADJ
SW3 to
SW1
PWM3 to
PWM1
VCC
VID7 to
VID0
VIDSEL
Exposed
Paddle
Ground. Biasing and logic output signals of the device are referenced to this ground.
Output Disable. This pin is actively pulled LOW when the EN input is low or when V_CC
is below the UVLO threshold, to disable the external MOSFET drivers.
FastvCore™ V_OS Adjustment Input. This signal is used as a control input for the
FastvCore™ circuit.
Switching Node Current Balance Inputs. Sense the switching side of the inductor
and used to measure the current level in each phase. The SW pins of unused phases
should be left open.
PWM Outputs. Each output is connected to the input of an external MOSFET driver,
such as the FAN5109. Connecting the PWM3 output to V_CC disables that phase,
allowing the FAN50FC3 to operate as a 2-phase controller.
Supply Voltage.
Voltage Identification Code Inputs. These digital inputs are connected to the internal
DAC and used to program the output voltage. These pins have 1µA internal pull-down;
if they are left open, the input state is decoded as logic LOW.
VID Table Select Input. A logic LOW selects the extended VR10 DAC table and a logic
HIGH selects the VR11 DAC table. This pin has a 1µA internal pull-down; if left open,
the input state is decoded as logic LOW.
Internally Connected to Die Ground. May be connected to ground or left floating.
Connect to ground for lowest package thermal resistance.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
4 of 21
www.fairchildsemi.com