FAN50FC3 Datasheet, PDF (18/21 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller

Dynamic VID
The FAN50FC3 has the ability to dynamically change
the VID inputs while the controller is running. This allows
the output voltage to change while the supply is running
and supplying current to the load. This is commonly
referred to as VID on-the-fly (OTF). A VID OTF can
occur under light or heavy load conditions. The
processor signals the controller by changing the VID
inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.
When a VID input changes state, the FAN50FC3
detects the change and ignores the DAC inputs for a
minimum of 200ns. This time prevents a false code due
to logic skew while the eight VID inputs are changing.
Additionally, the first VID change initiates the PWRGD
and CROWBAR blanking functions for a minimum of
100µs to prevent a false PWRGD or CROWBAR event.
Each VID change resets the internal timer.
Power Good Monitoring
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open-drain
output whose high level (when connected to a pull-up
resistor) indicates that the output voltage is within the
nominal limits specified based on the VID voltage
setting. PWRGD goes low if the output voltage is
outside of this specified range, if the VID DAC inputs are
in no CPU mode, or whenever the EN pin is pulled low.
PWRGD is blanked during a VID OTF event for a period
of ~200µs to prevent false signals during the time the
output is changing.
The PWRGD circuitry also incorporates an initial turn-on
delay time (TD5) based on the DELAY timer. Prior to the
SS voltage reaching the programmed VID DAC voltage,
100mV, the PWRGD pin is held low. Once the SS pin is
within 100mV of the programmed DAC voltage, the
capacitor on the DELAY pin begins to charge up. A
comparator monitors the DELAY voltage and enables
PWRGD when the voltage reaches 1.7V. The PWRGD
delay time is therefore set by a current of 15µA charging
a capacitor from 0V to 1.7V.
Output Crowbar
As part of the protection for the load and output
components of the supply, the PWM outputs are driven
low (turning on the low-side MOSFETs) when the output
voltage exceeds the upper crowbar threshold. This
crowbar action stops once the output voltage falls below
the release threshold of approximately 300mV.
Turning on the low-side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the
output over-voltage is due to a short in the high-side
MOSFET, this action current-limits the input supply,
protecting the microprocessor.
Output Enable and UVLO
For the FAN50FC3 to begin switching, the input supply
(V_CC) to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.85V
threshold. This initiates a system start-up sequence. If
either UVLO or EN is less than their respective
thresholds, the FAN50FC3 is disabled; which holds the
PWM outputs low, discharges the DELAY and SS
capacitors, and forces PWRGD and OD# signals low.
In the application circuit, the OD# pin should be
connected to the OD# inputs of the FAN5009 or
FAN5109 drivers. Pulling OD# LOW disables the drivers
such that both DRVH and DRVL are driven low. This
turns off the bottom MOSFETs to prevent them from
discharging the output capacitors through the output
inductors. If the bottom MOSFETs were left on, the
output capacitors could ring with the output inductors
and produce a negative output voltage to the processor.
NTC Resistance versus Temperature
Normalized to 25C
1.0
0.8
0.6
0.4
0.2
0.0
25
50
75
100
125
Temperature (C)
Figure 12. Typical NTC Resistance vs. Temperature
Applications and Component Selection
Please consult Fairchild Application Note:
AN-6052 — Instructions for the Multi-Phase VR11
MathCad^® Design Tool
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
18 of 21
www.fairchildsemi.com