FAN50FC3 Datasheet, PDF (15/21 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase FastvCore™ Buck Controller

Theory of Operation
Note: The values shown in this section are for reference
only. See the parametric tables for actual values.
The FAN50FC3 is a fixed-frequency PWM control with
multi-phase logic outputs for use in 2- and 3-phase
synchronous buck CPU power supplies. It has an
internal VID DAC designed to interface directly with 8-bit
VRD/VRM 11 and 7-bit VRD/VRM 10.x compatible
CPUs. Multiphase operation is required for the high
currents and low voltages of today’s microprocessors
that can require up to 150A of current.
The integrated features of the FAN50FC3 ensure a
stable, high-performance topology for:
ƒ Balanced currents and thermals between phases
ƒ High-speed response at the lowest possible
switching frequency and output decoupling
capacitors
ƒ Tight load line regulation and accuracy
ƒ High current output by allowing up to 3-phase
designs
ƒ Reduced output ripple due to multiphase operation
ƒ Good PC board layout noise immunity
ƒ Easily settable and adjustable design parameters
with simple component selection
ƒ 2- to 3-phase operation allows optimizing designs
for cost/performance and support a wide range of
applications.
Start-Up Sequence
The start-up sequence is shown in Figure 9. Once the
EN and UVLO conditions are met, the DELAY pin goes
through one cycle (TD1), after which, the internal
oscillator starts. The first two clock cycles are used for
phase detection. The soft-start ramp is then enabled
(TD2), raising the output voltage up to the boot voltage
of 1.1V. The boot hold time (TD3) allows the processor
VID pins to settle to the programmed VID code. After
TD3 timing is finished, the output soft starts, either up or
down, to the final VID voltage (during TD4). TD5 is the
time between the output reaching the VID voltage and
the PWRGD being presented to the system.
Phase-Detection Sequence
During start-up, the number of operational phases and
their phase relationship is determined by the internal
circuitry that monitors the PWM outputs. Normally, the
FAN50FC3 operates as a 3-phase PWM controller. For
2-phase operation, connect the PWM3 pin to V_CC.
The PWM logic, which is driven by the master oscillator,
directs the phase sequencer and channel detectors.
Channel detection is carried out during the first two clock
cycles after the chip is enabled. During the detection
period, PWM3 is connected to a 100µA sinking current
source and two internal voltage comparators check the
pin voltage of PWM3 versus a threshold of 3V typical. If
the pin is tied to V_IN, the pin voltage is above 3V and
that phase is disabled and put in a tri-state mode.
Otherwise, the internal 100µA current source pulls PWM
pin below the 3V threshold. After channel detection, the
current source is removed.
Shorting PWM3 to V_CC configures the system into 2-
phase operation.
12V V_IN
UVLO Threshold
V_TT
0.85V
DELAY
DELAY Threshold
SS
V_CC (Core)
V_Ready
TD1
1.0V
V_boot =1.1V
V_core = V_boot
V_core = VID
TD3 TD4 TD5
TD2
50µs
VIDs
Invalid
Valid
Figure 9. Start-Up Sequence Timing
After detection time is complete, the PWM outputs not
sensed as “pulled HIGH” function as normal PWM
outputs. PWM outputs sensed as “pulled HIGH” are put
into a high-impedance state.
The PWM signals are logic-level outputs intended for
driving external gate drivers, such as the FAN5109. Since
each phase is monitored independently; operation
approaching 100% duty cycle is possible. More than one
output can be on at the same time to allow phase overlap.
Master Clock Frequency
The clock frequency is set with an external resistor
connected from the RT pin to ground. The frequency-to-
resistor relationship is shown in the graph in Figure 6.
To determine the frequency per phase, divide the clock
by the number of enabled phases.
Output Current Sensing
The FAN50FC3 provides a dedicated current-sense
amplifier (CSA) to monitor the output current for proper
voltage positioning and for current limit detection (see
Figure 1). It differentially senses the voltage drop across
the DCR of the inductors to give the total average current
being delivered to the load. This method is inherently
more accurate than peak current detection or sampling
the voltage across the low-side MOSFETs. The CSA
implementation can be configured for the objectives of the
system. It can use output inductor DCR sensing without a
thermistor for lowest cost or output inductor DCR sensing
with a thermistor for improved accuracy with tracking of
inductor temperature.
© 2007 Fairchild Semiconductor Corporation
FAN50FC3 Rev. 1.0.0
15 of 21
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