FMS7951 Datasheet, PDF (3/8 Pages) Fairchild Semiconductor – Zero Delay Clock Multiplier

FMS7951
PRODUCT SPECIFICATION
Table 1. Functionality
REF_SEL
PLL_EN
OE
PLL
All Outputs
Input
0
0
1
By Pass
Hi-Z
PECL_CLK
0
0
0
By Pass
Running
PECL_CLK
0
1
0
Enabled
Running
PECL_CLK
1
0
1
By Pass
Hi-Z
TCLK
1
0
0
By Pass
Running
TCLK
1
1
0
Enabled
Running
TCLK
Table 2. Input Versus Output Frequency
DIV_SELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DIV_SELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DIV_SELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV_SELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note:
1. Reference input could be either PECL_CLK or TCLK input.
2. FBIN is tied to QD output for table
Table 3. Divide Select Functionality
DIV_SEL A
0
1
DIV_SEL B
0
1
DIV_SEL D
0
1
DIV_SEL D
0
1
QA
2XREF
4XREF
2XREF
4XREF
2XREF
4XREF
2XREF
4XREF
REF
2XREF
REF
2XREF
REF
2XREF
REF
2XREF
QB
REF
2XREF
REF
2XREF
1/2REF
REF
1/2REF
REF
REF
2XREF
REF
2XREF
1/2REF
REF
1/2REF
REF
QC
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
QA
QB
QC
÷2
÷4
÷4
÷4
÷8
÷8
QD
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
QD
÷4
÷8
REV. 1.0.0 1/9/01
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