FMS7951 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – Zero Delay Clock Multiplier

PRODUCT SPECIFICATION
Pin Assignments
VDDCOR
FBIN
DIV_SEL A
DIV_SEL B
DIV_SEL C
DIV_SEL D
GNDCOR
PECL_CLK
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
32-PIN
21
LQFP
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
QC0
VDDOUT
QC1
GNDOUT
QD0
VDDOUT
QD1
GNDOUT
FMS7951
Pin Description
Pin Name
VDDCOR
Pin #
1
Pin Type
PWR
FBIN
2
IN
DIV_SEL(A:D)
3, 4, 5, 6
IN
GNDCOR
7
PWR
PECL_CLK/
PECL_CLK
OE
8, 9
IN
10
IN
VDDOUT
11, 15, 19, 23, 27 PWR
QA; QB; QC(0:1); 12, 14, 16, 18, 20,
QD(0:4)
22, 24, 26, 28
GNDOUT
13, 17, 21, 25, 29
OUT
PWR
TCLK
30
IN
PLL_EN
REF_SEL
31
IN
32
IN
Description
Power Connection. Power supply for core logic and PLL
circuitry. Connect to 3.3 Volts nominal.
Feedback In. PLL feedback input. The user connects it to one of
the outputs.
Divider Select: It divides the clock to a desirable value. See
table 2. No internal pull up or pull down.
Ground Connection. Ground for core logic and PLL circuitry.
Connect to the common system ground plane.
PECL Clock Input: These are differential PECL inputs when
REF_SEL is Low, they are activated.
Output Enable. When high, all outputs are in high impedance.
Normal operation when asserted low.
Power Connection. Power supply for all the output buffers.
Connect to 3.3 Volts nominal.
Clock Outputs. These outputs are multiple of the input.
Ground Connection. Ground for all the outputs. Connect to
common system ground plane.
Test Clock. When PLL-EN is low, all outputs are buffer copy of
TCLK.
PLL Enable. When low, PLL is by passed.
Reference Select. When low, PECL_CLK/PECL_CLK is used
for input. When high, TCLK is used for input.
2
REV. 1.0.0 1/9/01