FAN7392_10 Datasheet, PDF (3/18 Pages) Fairchild Semiconductor – High-Current, High- and Low-Side, Gate-Drive IC

Internal Block Diagram
V_DD 9
HIN 10
LIN 12
SCHMITT
TRIGGER INPUT ^HS(ON/OFF)
UVLO
NOISE
CANCELLER
RR
SQ
UVLO
SD 11
CYCLE-By-CYCLE
EDGE TRIGGERED ^LS(ON/OFF)
SHUTDOWN
VSS/COM
LEVEL
SHIFT
DELAY
V_SS 13
Pin 4, 8, and 14 are no connection
Figure 3. Functional Block Diagram (Referenced 14-Pin)
V_DD 11
HIN 12
LIN 14
SCHMITT
TRIGGER INPUT ^HS(ON/OFF)
UVLO
NOISE
CANCELLER
RR
SQ
UVLO
SD 13
CYCLE-By-CYCLE
EDGE TRIGGERED ^LS(ON/OFF)
SHUTDOWN
VSS/COM
LEVEL
SHIFT
DELAY
V_SS 15
Pin 4, 5, 9,10 and 16 are no connection
Figure 4. Functional Block Diagram (Referenced 16-SOP)
6 V_B
7 HO
5 V_S
3 V_CC
1 _LO
2 COM
7 V_B
8 HO
6 V_S
3 V_CC
1 LO
2 COM
© 2009 Fairchild Semiconductor Corporation
FAN7392 Rev. 1.0.3
3
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