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FAN7392_10 Datasheet, PDF (14/18 Pages) Fairchild Semiconductor – High-Current, High- and Low-Side, Gate-Drive IC
Application Information
Negative VS Transient
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest diffi-
culty with this circuit is the negative voltage present at
the emitter of the high-side switching device when high-
side switch is turned-off in half-bridge application.
If the high-side switch, Q1, turns-off while the load cur-
rent is flowing to an inductive load, a current commuta-
tion occurs from high-side switch, Q1, to the diode, D2,
in parallel with the low-side switch of the same inverter
leg. Then the negative voltage present at the emitter of
the high-side switching device, just before the freewheel-
ing diode, D2, starts clamping, causes load current to
suddenly flow to the low-side freewheeling diode, D2, as
shown in Figure 34.
DC+ Bus
Q1
D1
iLOAD
ifreewheeling
VS
Load
Q2
D2
Figure 34. Half-Bridge Application Circuits
This negative voltage can be trouble for the gate driver’s
output stage, there is the possibility to develop an over-
voltage condition of the bootstrap capacitor, input signal
missing and latch-up problems because it directly affects
the source VS pin of the gate driver, as shown in Figure
35. This undershoot voltage is called “negative VS tran-
sient”.
Q1
GND
VS
GND
Freewheeling
Figure 35. VS Waveforms During Q1 Turn-Off
Figure 36 and Figure 37 show the commutation of the
load current between high-side switch, Q1, and low-side
freewheelling diode, D3, in same inverter leg. The para-
sitic inductances in the inverter circuit from the die wire
bonding to the PCB tracks are jumped together in LC and
LE for each IGBT. When the high-side switch, Q1, and
low-side switch, Q4, are turned on, the VS1 node is
below DC+ voltage by the voltage drops associated with
the power switch and the parasitic inductances of the cir-
cuit due to load current is flows from Q1 and Q4, as
shown in Figure 36. When the high-side switch, Q1, is
turned off and Q4, remained turned on, the load current
to flows the low-side freewheeling diode, D3, due to the
inductive load connected to VS1 as shown in Figure 37.
The current flows from ground (which is connected to the
COM pin of the gate driver) to the load and the negative
voltage present at the emitter of the high-side switching
device.
In this case, the COM pin of the gate driver is at a higher
potential than the VS pin due to the voltage drops associ-
ated with freewheeling diode, D3, and parasitic ele-
ments, LC3 and LE3.
DC+ Bus
LC1
VLC1
Q1
D1
LE1
VLE1
VS1
LC3
Q3
D3
iLOAD
ifreewheeling
Load
LC2
Q2
D2
LE2
VS2
VLC4 LC4
Q4
D4
LE3
VLE4 LE4
Figure 36. Q1 and Q4 Turn-On
DC+ Bus
LC1
Q1
D1
iLOAD
ifreewheeling
LE1
VS1
Load
LC3
VLC3
Q3
D3
LE3
VLE3
LC2
Q2
D2
LE2
VS2
VLC4 LC4
Q4
D4
VLE4 LE4
Figure 37. Q1 Turn-Off and D3 Conducting
© 2009 Fairchild Semiconductor Corporation
FAN7392 Rev. 1.0.3
14
www.fairchildsemi.com