FAN5234_10 Datasheet, PDF (3/15 Pages) Fairchild Semiconductor – Dual Mobile-Friendly PWM / PFM Controller

Pin Configuration
VIN
PGOOD
EN
ILIM
VOUT
VSEN
SS
AGND
1
16
2
15
3
14
4
13
FA N5234
5
12
6
11
7
10
8
9
FPWM
BOOT
HDRV
SW
ISNS
VCC
LDRV
PGND
Figure 3. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VIN
PGOOD
EN
ILIM
VOUT
VSEN
SS
AGND
PGND
LDRV
VCC
ISNS
SW
HDRV
BOOT
FPWM
Description
Input Voltage. Connect to main input power source (battery), also used to program
operating frequency for low input voltage operation (see Table 1).
Power-Good Flag. An open-drain output that pulls LOW when VSEN is outside of a ±10%
range of the 0.9V reference.
Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator
after a latched fault condition. This is a CMOS input whose state is indeterminate if left open.
Current Limit. A resistor from this pin to GND sets the current limit.
Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth
transition during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC.
Output Voltage Sense. The feedback from the output. Used for regulation as well as
power-good, under-voltage, and over-voltage protection monitoring.
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization, when this pin is charged with a 5µA current source.
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
Power Ground. The return for the low-side MOSFET driver output. Connect to the gate of
the low-side MOSFET.
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to the gate of the
low-side MOSFET.
Supply Voltage. This pin powers the chip as well as the LDRV buffers. The IC starts to
operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops
below 4.3V (UVLO falling).
Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
Switching Node. Return for the high-side MOSFET driver and a current-sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
High-Side Drive. High-side (upper) MOSFET driver output. Connect to the gate of the high-
side MOSFET.
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2.
Forced PWM Mode. When logic HIGH, inhibits the regulation from entering Hysteretic
Mode.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
3
www.fairchildsemi.com