FAN5234_10 Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – Dual Mobile-Friendly PWM / PFM Controller

High-Side Losses
Figure 9 shows a MOSFET's switching interval, with the
upper graph being the voltage and current on the drain-
to-source and the lower graph detailing VGS vs. time
with a constant current charging the gate. The x-axis
therefore is also representative of gate charge (QG).
CISS = CGD + CGS, and it controls t1, t2, and t4 timing.
CGD receives the current from the gate driver during t3
(as VDS is falling). The gate charge (QG) parameters on
the lower graph are either specified or can be derived
from MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses,
occur during the shaded time when the MOSFET has
voltage across it and current through it.
These losses are given by:
PUPPER = PSW + PCOND
(20)
where:
P
SW
=
⎜⎛
⎜⎝
V×
DS
2
I
L
×
2
×
t
s
⎟⎞
⎟⎠
f
SW
(21)
P
COND
=
⎜⎜⎝⎛
V
OUT
V_IN
⎟⎟⎠⎞ ^{× I} OUT
2
×R
DS( ON )
(22)
PUPPER is the upper MOSFET's total losses and PSW and
PCOND are the switching and conduction losses for a
given MOSFET. RDS(ON) is at the maximum junction
temperature (TJ). tS is the switching period (rise or fall
time) and is t2+t3 in Figure 9.
V_DS
C_ISS
C_GD
C_ISS
The driver’s impedance and CISS determine t2 while t3’s
period is controlled by the driver's impedance and QGD.
Since most of tS occurs when VGS = VSP, use a constant
current assumption for the driver to simplify the
calculation of tS:
Q
Q
t_s =
G(SW )
I
DRIVER
=
⎜⎛
G(SW )
V −V
CC
SP
⎟⎞
⎜⎝ _{R DRIVER}
+R
GATE
⎟⎠
(23)
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
QG(SW) = QGD + QGS – QTH
(24)
where QTH is the gate charge required to get the
MOSFET to its threshold (VTH).
For the high-side MOSFET, VDS = VIN, which can be as
high as 20V in a typical portable application. Care
should be taken to include the delivery of the
MOSFET's gate power (PGATE) in calculating the power
dissipation required for the FAN5234:
P =Q ×V ×f
G ATE
G
CC SW
(25)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2 switches on or off with its parallel Schottky diode
conducting; therefore, VDS≈0.5V. Since PSW is
proportional to VDS, Q2's switching losses are negligible
and Q2 is selected based on RDS(ON) only.
Conduction losses for Q2 are given by:
I_D
Q_GS
Q_GD
4.5V
V_SP
V_TH
V_GS
t1
Figure 9.
Q
G(SW)
t2
t3
t4
t5
Switching Losses and QG
(CISS = CGS || CGD)
V_IN
5V
C_GD
R_D
HDRV
R_GATE
G
C_GS
SW
Figure 10. Drive Equivalent Circuit
P = (1− D)×I ² × R
COND
OUT
DS( ON )
(26)
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature and
D = ^VOUT is the minimum duty cycle for the converter.
V_IN
Since DMIN <20% for portable computers, (1-D)≈1 produces
a conservative result, simplifying the calculation.
The maximum power dissipation (PD(MAX)) is a function
of the maximum allowable die temperature of the low-
side MOSFET, the ΘJA, and the maximum allowable
ambient temperature rise:
T −T
P
= ^J(MAX)
A (MAX )
D(MAX )
Θ_JA
(27)
ΘJA depends primarily on the amount of PCB area that
can be devoted to heat sinking (see AN-1029 —
Maximum Power Enhancement Techniques for SO-8
Power MOSFET for MOSFET thermal information).
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
12
www.fairchildsemi.com