FAN5234_10 Datasheet, PDF (13/15 Pages) Fairchild Semiconductor – Dual Mobile-Friendly PWM / PFM Controller

Table 2. Build Of Materials for 1.8V, 3.5A Regulator
Description
Qty.
Ref.
Vendor
Part Number
Capacitor 68μF, Tantalum, 25V, ESR 95mΩ
Capacitor 10nF, Ceramic
1
C1
2
C2, C3
AVX.
Any
TPSV686*025#095
Capacitor 68μF, Tantalum, 6V, ESR 1.8Ω
Capacitor 0.1μF, Ceramic
1
C4
2
C5
AVX.
Any
TAJV686*006
Capacitor 330μF, Tantalum, 6V, ESR 100mΩ
2
C6
AVX.
TPSE337*006#0100
1.82KΩ, 1% Resistor
2
R1, R2
Any
1.3KΩ, 1% Resistor
1
R3
Any
100KΩ, 5% Resistor
1
R4
Any
56.2KΩ, 1% Resistor
Schottky Diode; 0.5A, 20V
Inductor 8.4μH, 6A
Dual MOSFET with Schottky
1
R5
Any
2
D1 Fairchild Semiconductor
MBR05S0L
1
L1
Any
1
Q
Fairchild Semiconductor FDS6986AS⁽¹⁾
PWM Controller
1
U1 Fairchild Semiconductor
FAN5234
Note:
1. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the
Power MOSFET Selection Section and AN-6002 for design calculations.
Layout Considerations
Switching converters, even during normal operation,
produce short pulses of current that could cause
substantial ringing and be a source of EMI if layout
constrains are not observed.
There are two sets of critical components in a DC-DC
converter. The switching power components process
large amounts of energy at high rate and are noise
generators. The low-power components responsible for
bias and feedback functions are sensitive to noise.
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt
voltage swing; such as SW, HDRV, and LDRV. All
surrounding circuitry tends to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place
traces connected to the feedback components adjacent
to these traces. It is not recommended to use high
density interconnect systems, or micro-vias, on these
signals. The use of blind or buried vias should be
limited to the low-current signals only. The use of
normal thermal vias is at the discretion of the designer.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of
handling peak currents of 2A. Minimize the area within
the gate-source path to reduce stray inductance and
eliminate parasitic ringing at the gate.
Locate small critical components, like the soft-start
capacitor and current sense resistors, as close as
possible to the respective pins of the IC.
The FAN5234 utilizes advanced packaging
technologies with lead pitches of 0.6mm. High-
performance analog semiconductors utilizing narrow
lead spacing may require special considerations in
PWB design and manufacturing. It is critical to maintain
proper cleanliness of the area surrounding these
devices. It is not recommended to use any type of rosin
or acid core solder, or the use of flux, in either the
manufacturing or touch up process as these may
contribute to corrosion or enable electro-migration and /
or eddy currents near the sensitive low-current signals.
When chemicals are used on or near the PWB, it is
suggested that the entire PWB be cleaned and dried
completely before applying power.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
13
www.fairchildsemi.com