FAN2315MPX Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – FAN2315 TinyBuck 15 A Integrated Synchronous Buck Regulator

Printed Circuit Board (PCB) Layout Guidelines
The following points should be considered before
beginning a PCB layout using the FAN2315. A sample
PCB layout from the TinyBuck™ evaluation board is
shown in Figure 24 through Figure 27 following the
layout guidelines.
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
Power components consisting of input capacitors,
output capacitors, inductor, and TinyBuck devices
should be placed on a common side of the PCB in
close proximity to each other and connected using
surface copper.
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the high-
voltage switching circuits such as SW and BOOT, and
connected to their respective pins with short traces.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and low-
side MOSFET source to the PGND region under the
power portion of the IC.
The SW node trace which connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
The inner PCB layer closest to the TinyBuck device
should have Power Ground (PGND) under the power
processing portion of the device (PVIN, SW, and
PGND). This inner PCB layer should have a separate
Analog Ground (AGND) under the P1 pad and the
associated analog components. AGND and PGND
should be connected together near the IC between
PGND pins 18-21 and AGND pin 23 which connects to
P1 thermal pad.
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25 mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the TinyBuck device.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor, and coupling
capacitor C5 should be placed near FB pin to minimize
FB pin trace length.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple injection
resistor R2 should be made through separate traces.
© 2011 Fairchild Semiconductor Corporation
FAN2315 • Rev. 1.0.4
15
www.fairchildsemi.com