FAN2315MPX Datasheet, PDF (12/19 Pages) Fairchild Semiconductor – FAN2315 TinyBuck 15 A Integrated Synchronous Buck Regulator

The soft-start option can be used for ratiometric tracking.
When EN is LOW, the soft-start capacitor is discharged.
Startup on Pre-Bias
FAN2315 allows the regulator to start on a pre-bias
output, V_OUT, and ensures V_OUT is not discharged during
the soft-start operation.
To guarantee no glitches on V_OUT at the beginning of the
soft-start ramp, the LS is disabled until the first positive-
going edge of the PWM signal. The regulator is also
forced into PFM Mode during soft-start to ensure the
inductor current remains positive, reducing the
possibility of discharging the output voltage.
PVCC
The FAN2315 requires an external source connected to
PVCC to supply power to the internal gate drivers. The
PVCC pin should be bypassed with a 2.2 µF ceramic
capacitor.
V_CC Bias Supply and UVLO
The V_CC rail supplies power to the controller. It is
generally connected to the PVCC rail through a low-
pass filter of a 10 Ω resistor and 0.1 μF capacitor to
minimize any noise sources from the driver supply.
An Under-Voltage Lockout (UVLO) circuit monitors the
V_CC voltage to ensure proper operation. Once the V_CC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or V_IN rails.
Pulse Frequency Modulation (PFM)
One of the key benefits of using a constant on-time
modulation scheme is the seamless transitions in and
out of Pulse Frequency Modulation (PFM) Mode. The
PWM signal is not slave to a fixed oscillator and,
therefore, can operate at any frequency below the target
steady-state frequency. By reducing the frequency
during light-load conditions, the efficiency can be
significantly improved.
The FAN2315 provides a Zero-Crossing Detector (ZCD)
circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load,
the LS MOSFET is turned off around the zero crossing
to eliminate negative current in the inductor. For
predictable operation entering PFM mode the controller
waits for nine consecutive zero crossings before
allowing the LS MOSFET to turn off.
In PFM Mode, f_SW varies or modulates proportionally to
the load; as load decreases, f_SW also decreases. The
switching frequency, while the regulator is operating in
PFM, can be expressed as:
=
2× ×
×( −
)×
(6)
where L is inductance and I_OUT is output load current.
Minimum Frequency Clamp
To maintain a switching frequency above the audible
range, the FAN2315 clamps the switching frequency to
a minimum value of 18 kHz. The LS MOSFET is turned
on to discharge the output and trigger a new PWM
cycle. The minimum frequency clamp is disabled during
soft-start.
Protection Features
The converter output is monitored and protected against
over-current, over-voltage, under-voltage, and high-
temperature conditions.
Over-Current Protection (OCP)
The FAN2315 uses current information through the LS
to implement valley-current limiting. While an OC event
is detected, the HS is prevented from turning on and the
LS is kept on until the current falls below the user-
defined set point. Once the current is below the set
point, the HS is allowed to turn on.
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
40 mV and the on-time is fixed at the steady-state
duration. By nature of the control method; as V_OUT drops,
the switching frequency is lower due to the reduced rate
of inductor current decay during the off-time.
The ILIM pin has an open-detection circuit to provide
protection against operation without a current limit.
Under-Voltage Protection (UVP)
If V_FB is below the under-voltage threshold of -11% V_REF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over-Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an OV event, PGOOD pulls LOW.
When V_FB is > +11% of V_REF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, V_OUT
overshoot can be reduced when there is positive
inductor current by increasing the rate of discharge.
Once the V_FB voltage falls below V_REF, the latched OV
signal is cleared and operation returns to normal.
A second over-voltage detection is implemented to
protect the load from more serious failure. When V_FB
rises +22% above the V_REF (732 mV), the HS turns off,
but the LS is forced on until a power cycle on VCC.
Over-Temperature Protection (OTP)
FAN2315 incorporates an over-temperature protection
circuit that disables the converter when the die
temperature reaches 155°C. The IC restarts when the
die temperature falls below 140°C.
Power Good (PGOOD)
The PGOOD pin serves as an indication to the system
that the output voltage of the regulator is stable and
within regulation. Whenever V_OUT is outside the
regulation window or the regulator is at over-
temperature (UV, OV, and OT), the PGOOD pin is
pulled LOW.
PGOOD is an open-drain output that asserts LOW when
V_OUT is out of regulation or when OT is detected.
© 2011 Fairchild Semiconductor Corporation
FAN2315 • Rev. 1.0.4
12
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