FXLP4555MPX Datasheet, PDF (11/13 Pages) Fairchild Semiconductor – 1.8V / 3.0V SIM Card Power Supply and Level Shifter

Applications Information (Continued)
Input Schmitt Triggers
All the logic input pins (except I/O_H and I/O_C) have
built-in Schmitt trigger circuits to prevent uncontrolled
operation. Typical dynamic characteristics of the related
pins are depicted in Figure 11.
The output signal is guaranteed to go HIGH when the
input voltage is above 0.7 x V_DD and go LOW when the
input voltage is below 0.4V. See Electrical
Characteristics section.
Shutdown Operating
To save power, it is possible to put the FXLP4555 in
Shutdown Mode by setting the pin EN LOW. The device
enters Shutdown Mode automatically when V_CCA goes
lower than 1.1V typically.
ESD Protection
The FXLP4555 SIM interface features an HBM ESD
voltage protection in excess of 7kV for all the SIM pins
(IO_C, CLK_C, RST_C, VCC_C and GND). All the other
pins (Host side) sustain at least 2kV. The HBM ESD
voltage required by the ISO7816 standard is 4kV.
Printed Circuit Board (PCB) Layout
Careful layout routing should be applied to achieve
efficient operating of the device in its mobile or portable
environment and to fully exploit its performance.
The bypass capacitors must be connected as close as
possible to the device pins (VCC_C, VCCA, or VBAT) to
reduce possible parasitic behaviors (ripple and noise). It
is recommended to use ceramic capacitors.
The exposed pad should be connected to ground as
well as the unconnected pins (NC). A relatively large
ground plane is recommended.
Clock Stop
Section 6.3.2 of ISO7816-3 identifies the “Power
Management” feature of Clock Stop. For cards
supporting Clock Stop, when the interface device
expects no transmission from the card and when I/O
has remained at state H for at least 1,860 clock cycles
(delay t_g), then according to Figure 13, the interface
device may stop the clock on CLK (at time t_e) while the
SIM card V_CC remains powered and RST at state H.
Figure 12.
When the clock is stopped (from time t_e to time t_f), CLK
shall be maintained either at state H or at state L,
according to the clock stop indicator X defined in section
8.3 of the ISO7816-3 specification.
At time t_f, the interface device restarts the clock and the
information exchange on I/O may continue after at least
700 clock cycles (at time t_f + t_h).
Clock Stop
The FXLP4555 supports the above description of Clock
Stop per ISO7816-3 specifications.
© 2010 Fairchild Semiconductor Corporation
FXLP4555 • Rev. 1.0.0
11
www.fairchildsemi.com