FAN48632 Datasheet, PDF (10/13 Pages) Fairchild Semiconductor – 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost

Bypass Operation
In normal operation, the device automatically transitions from
Boost Mode to Bypass Mode, if VIN goes above target VOUT. In
Bypass Mode, the device fully enhances both Q1 and Q3 to
provide a very low impedance path from VIN to VOUT. Entry to
the Bypass Mode is triggered by condition where VIN > VOUT
and no switching has occurred during past 5 µs. To soften the
entry to Bypass Mode, Q3 is driven as a linear current source
for the first 5 µs. Bypass Mode exit is triggered when VOUT
reaches the target VOUT voltage. During Automatic Bypass
Mode, the device is short-circuit protected by voltage
comparator tracking the voltage drop from VIN to VOUT; if the
drop exceeds 200 mV, a FAULT is declared.
With sufficient load to enforce CCM operation, the Bypass
Mode to Boost Mode transition occurs at the target VOUT. The
corresponding input voltage at the transition point is:
V_IN  V_OUT  I _LOAD  (DCR_L  R_{DS(ON )P} ) || R_{DS(ON )BYP}
EQ. 1
The Bypass Mode entry threshold has 25 mV hysteresis
imposed at VOUT to prevent cycling between modes. The
transition from Boost Mode to Bypass Mode occurs at the
target VOUT+25 mV. The corresponding input voltage is:
V_IN  V_OUT  25mV  I_LOAD  (DCR_L  R_DS(ON)P ) EQ. 2
Forced Bypass
Entry to Forced Bypass Mode initiates with a current limit on
Q3 and then proceeds to a true bypass state. To prevent
reverse current to the battery, the device waits until output
discharges below VIN before entering Forced Bypass Mode.
Low-IQ Forced Bypass Mode is available for the FAN48632.
After the transition is complete, most of the internal circuitry is
disabled to minimize quiescent current draw. OCP, UVLO,
output OVP and over-temperature protections are inactive in
Forced Bypass Mode.
In Forced Bypass Mode, VOUT can follow VIN below VOUT(MIN).
VSEL
VSEL can be asserted in anticipation of a positive load
transient. Raising VSEL increases VOUT(MIN) by a fixed amount
and VOUT is stepped to the corresponding target output voltage
in 20 µs. The functionality can also be utilized to mitigate
undershoot during severe line transients, while minimizing
VOUT during more benign operating conditions to save power.
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
10
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