SI4925DY Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Dual P-Channel, Logic Level, PowerTrench MOSFET

January 2001
Si4925DY
Dual P-Channel, Logic Level, PowerTrench^® MOSFET
General Description
These P-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize the
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
Features
-6 A, -30 V. R_DS(ON) = 0.032 Ω @ V_GS = -10 V,
R_DS(ON) = 0.045 Ω @ V_GS = -4.5 V.
Low gate charge (14.5nC typical).
High performance trench technology for extremely low
R_DS(ON).
High power and current handling capability.
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
D2
D2
D1
D1
4925
SO-8
G2
S2
pin 1
G1
S1
SO-8
SOT-223
5
6
7
8
Absolute Maximum Ratings
Symbol Parameter
T_A = 25^oC unless otherwise noted
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Power Dissipation for Dual Operation
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
© 2001 Fairchild Semiconductor International
Si4925DY
-30
±20
-6
-20
2
1.6
1
0.9
-55 to 150
78
40
SOIC-16
4
3
2
1
Units
V
V
A
W
°C
°C/W
°C/W
Si4925DY Rev.A