XRT75R03D Datasheet, PDF (93/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER

XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.2
9.3 TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS_n pins “High” or in Host
mode by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, the
Transmit Section generates and transmits a continuous AMI all “1’s” pattern on TTIP_n and TRING_n pins. The
frequency of this “1’s” pattern is determined by TClk_n.TAOS data path is shown in Figure 29. TAOS does not
operate in Analog loopback or Remote Digital loopback mode. It will function in Digital loopback mode.
FIGURE 30. TRANSMIT ALL ONES (TAOS)
TCLK
TPDATA
TNDATA
1
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TAOS
TTIP
Tx
Transmit All 1
TRING
RCLK
RPOS
RNEG
1
HDB3/B3ZS
DECODER
DATA &
CLOCK
Rx
RECOVERY
1 _{if enabled}
2 _{if enabled and selected in either Receive or}
Transmit path
RTIP
RRING
10.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75R03D
The XRT75R03D LIU IC is very similar to the XRT75R03 in that they are both 3-Channel DS3/E3/STS-1 LIU
devices that also contain Jitter Attenuator blocks within each of the three channels. They are also pin to pin
compatible with each other. However, the Jitter Attenuators within the XRT75R03D has some enhancements
over and above those within the XRT75R03 (non-D) device. The Jitter Attenuator blocks within the
XRT75R03D will support all of the modes and features that exist in the XRT75R03 (non-D) device and in
addition they also support a SONET/SDH De-Sync Mode not available within the XRT75R03.
NOTE: The "D" suffix within the part number, XRT75R03D stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks in the XRT75R03D permits the user to design
a SONET/SDH PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and
Wander requirements.
• For SONET Applications
s Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications)
s ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
• For SDH Applications
s Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
Specifically, if the user designs in the XRT75R03D along with a SONET/SDH Mapper IC (which can be
realized as either a standard product or as a custom logic solution, in an ASIC or FPGA), then the followind can
be accomplished;
• The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
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