XRT75R03D Datasheet, PDF (51/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER

XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.2
FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3.
Noise Generator N
Attenuator 1
Attenuator 2
S
Signal Source
23
2 -1 PRBS
Cable Simulator
∑
DUT
XRT75R03D
Test Equipment
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE
E3
DS3
STS-1
CABLE LENGTH (ATTENUATION)
0 dB
12 dB
0 feet
225 feet
450 feet
0 feet
225 feet
450 feet
INTERFERENCE TOLERANCE
Equalizer “IN”
-17 dB
-14 gB
-15 dB
-15 dB
-14 dB
-15 dB
-14 dB
-14 dB
6.2 Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
TRAINING MODE:
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of
Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the RLOL_n bit
to “1” in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the
reference clock applied on ExClk_n pins.
DATA/CLOCK RECOVERY MODE:
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
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