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XRT75R03D Datasheet, PDF (6/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03D
REV. 1.0.2 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
THE PER-CHANNEL REGISTERS .......................................................................................................... 64
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F) ........................................ 64
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER
ATTENUATOR IC ................................................................................................................................. 64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 .................. 66
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 .................. 68
TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03 ................................................ 70
TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ......................................... 75
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ........................................... 78
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ......................................... 80
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ......................... 83
9.0 Diagnostic Features: ........................................................................................................................ 85
9.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 85
9.2 LOOPBACKS: ............................................................................................................................................... 85
9.2.1 ANALOG LOOPBACK: ....................................................................................................................... 85
Figure 26. PRBS MODE ................................................................................................................................. 85
Figure 27. Analog Loopback ........................................................................................................................... 86
9.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 87
9.2.3 REMOTE LOOPBACK: ....................................................................................................................... 87
Figure 28. Digital Loopback ............................................................................................................................ 87
Figure 29. Remote Loopback .......................................................................................................................... 87
9.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 88
10.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75R03D ............................................ 88
Figure 30. Transmit All Ones (TAOS) ............................................................................................................. 88
10.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................ 89
Figure 31. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network
90
10.2 MAPPING/DE-MAPPING JITTER/WANDER .............................................................................................. 91
10.2.1 HOW DS3 DATA IS MAPPED INTO SONET .................................................................................... 91
Figure 32. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 92
Figure 33. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes
Designated .................................................................................................................................... 93
Figure 34. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 94
Figure 35. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 95
Figure 36. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 96
Figure 37. An Illustration of Telcordia GR-253-CORE’s Recommendation on how map DS3 data into an STS-1
SPE ............................................................................................................................................... 97
Figure 38. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE’s Recommendation on how to map
DS3 data into an STS-1 SPE ........................................................................................................ 97
10.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits .......................................... 98
Figure 39. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 99
Figure 40. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in
a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal .......................... 100
10.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ........................................................................................ 102
10.3.1 The Concept of an STS-1 SPE Pointer ......................................................................................... 102
Figure 41. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a
DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal .............................. 102
Figure 42. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ..................... 103
10.3.2 Pointer Adjustments within the SONET Network ........................................................................ 104
Figure 43. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the
location of the J1 byte, designated ............................................................................................. 104
Figure 44. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1
and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ...
104
10.3.3 Causes of Pointer Adjustments .................................................................................................... 105
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