XRT75R03D Datasheet, PDF (7/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER

XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.2
Figure 45. An Illustration of an STS-1 signal being processed via a Slip Buffer .......................................... 106
Figure 46. An Illustration of the Bit Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "I"
bits designated ........................................................................................................................... 107
Figure 47. An Illustration of the Bit-Format within the 16-bit word (consisting of the H1 and H2 bytes) with the
"D" bits designated ..................................................................................................................... 108
10.3.4 Why are we talking about Pointer Adjustments? ........................................................................ 109
10.4 CLOCK GAPPING JITTER .............................................................................................................................. 109
Figure 48. Illustration of the Typical Applications for the XRT75R03D in a SONET De-Sync Application ... 109
10.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP-
PLICATIONS ........................................................................................................................................................................ 110
TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS .................................................................................................................................. 110
10.5.1 DS3 De-Mapping Jitter ................................................................................................................... 111
10.5.2 Single Pointer Adjustment ............................................................................................................ 111
Figure 49. Illustration of Single Pointer Adjustment Scenario ...................................................................... 111
10.5.3 Pointer Burst .................................................................................................................................. 112
10.5.4 Phase Transients ........................................................................................................................... 112
Figure 50. Illustration of Burst of Pointer Adjustment Scenario .................................................................... 112
Figure 51. Illustration of "Phase-Transient" Pointer Adjustment Scenario ................................................... 112
10.5.5 87-3 Pattern .................................................................................................................................... 113
10.5.6 87-3 Add .......................................................................................................................................... 113
Figure 52. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................. 113
10.5.7 87-3 Cancel ..................................................................................................................................... 114
Figure 53. Illustration of the 87-3 Add Pointer Adjustment Pattern .............................................................. 114
Figure 54. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................. 114
10.5.8 Continuous Pattern ........................................................................................................................ 115
10.5.9 Continuous Add ............................................................................................................................ 115
Figure 55. Illustration of Continuous Periodic Pointer Adjustment Scenario ............................................... 115
10.5.10 Continuous Cancel ...................................................................................................................... 116
Figure 56. Illustration of Continuous-Add Pointer Adjustment Scenario ....................................................... 116
Figure 57. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................. 116
10.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ........................................... 117
10.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE XRT75R03D IN A TYPICAL SYSTEM AP-
PLICATION .......................................................................................................................................................................... 117
10.7.1 Intrinsic Jitter Test results ............................................................................................................ 117
TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..... 117
10.7.2 Wander Measurement Test Results ............................................................................................. 118
10.8 DESIGNING WITH THE XRT75R03D .............................................................................................................. 118
10.8.1 How to design and configure the XRT75R03D to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements ..................................................................................................................... 118
Figure 58. Illustration of the XRT75R03D being connected to a Mapper IC for SONET De-Sync Applications ..
118
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 119
CHANNEL 1 ADDRESS LOCATION = 0X0E ......................................... 119
CHANNEL 2 ADDRESS LOCATION = 0X16 ......................................... 119
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 120
CHANNEL 1 ADDRESS LOCATION = 0X0E .............................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................... 120
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ............................... 120
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................. 120
10.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior
to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75R03D .......................................... 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................ 121
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................ 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
IV