XRT86VL38 Datasheet, PDF(90/180 Page) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO

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XRT86VL38 Datasheet, PDF (90/180 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

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XRT86VL38

PRELIMINARY

OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

REV. P1.0.9

TABLE 67: TRANSMIT SIGNALING CONTROL REGISTER 0-31 (TSCR 0-31)

HEX ADDRESS: 0Xn340 TO 0XN35F

BIT

FUNCTION

TYPE DEFAULT

DESCRIPTION-OPERATION

7 A (x)

R/W See Note Transmit Signaling bit A or x bit

This bit allows users to provide signaling Bit A for octets 0-31 if

Channel Associated Signaling (CAS) is enabled and if signaling

data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this

NOTE:

Users must write to TSCR0 (Address 0xn340) the correct

CAS alignment bits (0 bits) in order to get CAS SYNC at the

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xn350) and programming the

TxSIGSRC[1:0] bits within this register to âb11â.

6 B (y)

R/W See Note Transmit Signaling bit B or y bit

This bit allows users to provide signaling Bit B for octets 0-31 if

Channel Associated Signaling (CAS) is enabled and if signaling

data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this

NOTE:

Users must write to TSCR0 (Address 0xn340) the correct

CAS alignment bits (0 bits) in order to get CAS SYNC at the

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xn350) and programming the

TxSIGSRC[1:0] bits within this register to âb11â.

5 C (x)

R/W See Note Transmit Signaling bit C or x bit

This bit allows users to provide signaling Bit C for octets 0-31 if

Channel Associated Signaling (CAS) is enabled and if signaling

data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this

NOTE:

Users must write to TSCR0 (Address 0xn340) the correct

CAS alignment bits (0 bits) in order to get CAS SYNC at the

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xn350) and programming the

TxSIGSRC[1:0] bits within this register to âb11â.

4 D (x)

R/W See Note Transmit Signaling bit D or x bit

This bit allows users to provide signaling Bit D in for octets 0-31 if

Channel Associated Signaling (CAS) is enabled and if signaling

data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this

NOTE:

Users must write to TSCR0 (Address 0xn340) the correct

CAS alignment bits (0 bits) in order to get CAS SYNC at the

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xn350) and programming the

TxSIGSRC[1:0] bits within this register to âb11â.

3 Reserved

- See Note Reserved

2 Reserved

- See Note Reserved

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