XRT86VL38 Datasheet, PDF (111/180 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

REV. P1.0.9
PRELIMINARY
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 96: BLOCK INTERRUPT ENABLE REGISTER (BIER)
HEX ADDRESS: 0XnB01
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 SA6_ENB
R/W
0
SA6 Block interrupt enable
This bit permits the user to either enable or disable the SA 6 Block
for interrupt generation.
If the user writes a “0” to this register bit and disables the SA 6 Block
for interrupt generation, then all SA 6 interrupts will be disabled for
interrupt generation.
If the user writes a “1” to this register bit, the SA6 Block interrupt at
the “Block Level” will be enabled. However, the individual SA 6 inter-
rupts at the “Source Level” still need to be enabled in order to gener-
ate that particular interrupt to the interrupt pin.
0 - Disables all SA6 Block interrupt within the device.
1 - Enables the SA6 interrupt at the “Block-Level”.
6 Reserved
For T1 mode only
5 RXCLKLOSS
R/W
0
Loss of Recovered Clock Interrupt Enable
This bit permits the user to either enable or disable the Loss of
Recovered Clock Interrupt for interrupt generation.
0 - Disables the Loss of Recovered Clock Interrupt within the device.
1 - Enables the Loss of Recovered Clock interrupt at the “Source-
Level”.
4 ONESEC_ENB
R/W
0
One Second Interrupt Enable
This bit permits the user to either enable or disable the One Second
Interrupt for interrupt generation.
0 - Disables the One Second Interrupt within the device.
1 - Enables the One Second interrupt at the “Source-Level”.
3 HDLC_ENB
R/W
0
HDLC Block Interrupt Enable
This bit permits the user to either enable or disable the HDLC Block
for interrupt generation.
If the user writes a “0” to this register bit and disables the HDLC
Block for interrupt generation, then all HDLC interrupts will be dis-
abled for interrupt generation.
If the user writes a “1” to this register bit, the HDLC Block interrupt at
the “Block Level” will be enabled. However, the individual HDLC
interrupts at the “Source Level” still need to be enabled in order to
generate that particular interrupt to the interrupt pin.
0 - Disables all SA6 Block interrupt within the device.
1 - Enables the SA6 interrupt at the “Block-Level”.
2 SLIP_ENB
R/W
0
Slip Buffer Block Interrupt Enable
This bit permits the user to either enable or disable the Slip Buffer
Block for interrupt generation.
If the user writes a “0” to this register bit and disables the Slip Buffer
Block for interrupt generation, then all Slip Buffer interrupts will be
disabled for interrupt generation.
If the user writes a “1” to this register bit, the Slip Buffer Block inter-
rupt at the “Block Level” will be enabled. However, the individual Slip
Buffer interrupts at the “Source Level” still need to be enabled in
order to generate that particular interrupt to the interrupt pin.
0 - Disables all Slip Buffer Block interrupt within the device.
1 - Enables the Slip Buffer interrupt at the “Block-Level”.
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