XR19L220_07 Datasheet, PDF (9/43 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

REV. 1.0.1
XR19L220
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
FIGURE 5. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL and DLM
Registers
MCR Bit-7=0
(default)
Baud Rate
Generator
Logic
MCR Bit-7=1
16X
Sampling
Rate Clock to
Transmitter
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
MCR Bit-7=1
MCR Bit-7=0 ^{DIVISOR FOR 16x DIVISOR FOR 16x}
Clock (Decimal) Clock (HEX)
(DEFAULT)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
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